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參數(shù)資料
| 型號： | FW802A-DB |
| 英文描述： | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| 中文描述： | 低功耗PHY的IEEE 1394A端口- 2000兩線收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 461K |
| 代理商： | FW802A-DB |
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Intel
80200 Processor based on Intel
XScale
Microarchitecture
Functional Overview
12
August 2002
Datasheet
2.11
Clock and Power Management
The Intel
80200 processor was designed with power saving techniques that power-up a functional
block only when it is needed. Low power modes are selectable by programming CP 14, register 6.
The Intel
80200 processor was designed to allow dynamic clocking. The core clock frequency is
set by programming CP14, Register 7. This enables software to conserve power by matching the
core clock frequency to the current workload.
2.12
Performance Monitoring Unit (PMU)
The Performance Monitoring Unit contains two 32-bit event counters and one 32-bit clock counter.
The event counters can be programmed to monitor i-cache hit rate, data caches hit rate, ITLB hit
rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count.
2.13
Debug Unit
The Debug Unit is accessed through the JTAG port. The industry-standard IEEE1149.1 JTAG port
consists of a Test Access Port (TAP) controller, Boundary-Scan register, instruction and data
registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#. The debug unit, when used
with debugger application code running on a host system outside of the Intel
80200 processor,
allows a program running on the Intel
80200 processor to be debugged. It allows the debugger
application code or a debug exception to stop program execution and re-direct execution to a debug
handling routine. Debug exceptions are instruction breakpoint, data breakpoint, software
breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once
execution has stopped, the debugger application code can examine or modify the core’s state,
co-processor state, or memory. The debugger application code can then restart program execution.
The debug unit has two hardware instruction breakpoint registers, two hardware data breakpoint
registers, and a hardware data breakpoint control register. The second data breakpoint register can
be alternatively used as a mask register for the first data breakpoint register. A 256-entry trace
buffer provides the ability to capture control flow messages or addresses. A JTAG instruction
(LDIC) can be used to download a debug handler via the JTAG port to the mini-instruction cache
(the i-cache has a 2 KByte mini-instruction cache, like the mini-data cache, that is used only to
hold a debug handler).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW802C | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW802C-DB | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW803-09-DB | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW803 | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW804-09-DB | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW802B | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE㈢ 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802B-DB | 制造商:Legerity 功能描述:DUAL LINE TRANSCEIVER, PQFP64 |
| FW802BF | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device |
| FW802BF-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device |
| FW802C | 制造商:AGERE 制造商全稱:AGERE 功能描述:FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
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