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| 型號(hào)： | FW802A-DB |
| 英文描述： | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| 中文描述： | 低功耗PHY的IEEE 1394A端口- 2000兩線收發(fā)器/仲裁器裝置 |
| 文件頁(yè)數(shù)： | 13/36頁(yè) |
| 文件大?。?/td> | 461K |
| 代理商： | FW802A-DB |
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Intel
80200 Processor based on Intel
XScale
Microarchitecture
Package Information
Datasheet
August 2002
13
3.0
Package Information
3.1
Package Introduction
The Intel
80200 processor is offered in a Plastic Ball Grid Array (PBGA) package. See
Figure 2
“241-Lead PBGA Package” on page 17
.
3.1.1
Functional Signal Definitions
This section defines the pins and signals in the following tables:
Table 2 “Pin Description Nomenclature” on page 13
Table 3 “Power Pins” on page 14
Table 4 “Signal Pin Description” on page 14
Table 5 “JTAG Pins” on page 16
3.1.1.1
Signal Pin Descriptions
Table 2.
Pin Description Nomenclature
Symbol
Description
I
Input pin only
Output pin only
Pin can be either an input or output
Pin must be connected as described
NO CONNECT. Do not make electrical connections to these balls.
While the
RESETOUT#
pin is asserted, the pin:
Rst(1) Is driven to Vcc
Rst(0) Is driven to Vss
Rst(X) Is driven to unspecified state (1 or 0, buses may contain a mix of 1 and 0 signals)
Rst(H) Is pulled up to Vcc
Rst(L) Is pulled down to Vss
Rst(Z) Floats
Rst(Q) Is a valid output
Since RESET# is asynchronous, these are asynchronous events.
While the Intel
80200 processor is in HOLD mode (
HOLD
asserted and took effect), the pin:
Hld(Z) Floats
Hld(Q) is a valid output
Hld(1) is driven to Vcc
Note: When both
HLDA
and
RESETOUT#
are asserted, then HOLD mode takes priority; the
output pins assume the state specified by Hld(...). The
HOLD
pin is also honored during Idle
and Sleep modes; the output pins assume the state specified by Hld(...).
While the Intel
80200 processor is in Idle or Sleep mode (software selected), pin:
Slp(1) Is driven to Vcc
Slp(0) Is driven to Vss
Slp(X) Is driven to unspecified state
Slp(Q) Is a valid output
O
I/O
-
N/C
Rst(...)
Hld(...)
Slp(...)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW802C | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW802C-DB | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW803-09-DB | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW803 | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW804-09-DB | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW802B | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE㈢ 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802B-DB | 制造商:Legerity 功能描述:DUAL LINE TRANSCEIVER, PQFP64 |
| FW802BF | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device |
| FW802BF-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device |
| FW802C | 制造商:AGERE 制造商全稱:AGERE 功能描述:FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
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