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參數(shù)資料
| 型號： | FW802A-DB |
| 英文描述： | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| 中文描述： | 低功耗PHY的IEEE 1394A端口- 2000兩線收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 461K |
| 代理商： | FW802A-DB |
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Intel
80200 Processor based on Intel
XScale
Microarchitecture
Package Information
14
August 2002
Datasheet
Table 3.
Power Pins
Name
Count
Description
V
CC
17
Positive supply for the core.
V
SS
70
Ground.
V
CCP
25
Positive supply for the I/O pins.
V
CCA
1
Positive supply for the analog circuitry (PLL).
Table 4.
Signal Pin Description (Sheet 1 of 2)
Name
Count
Type
Description
A[15:0]
16
O
Rst(X)
Hld(Z)
Slp(X)
Address Bus
: Conveys either the upper or lower half of a 32-bit
address during the issue phase of a bus transaction.
ABORT
1
I
Abort Transaction
: When asserted during the data phase of a
transaction, this signal causes the remainder of that transaction to
be aborted.
ADS#/LEN[2]
1
O
Rst(1)
Hld(Z)
Slp(1)
Address Strobe/Length
:
During the first cycle of the issue phase, this signal indicates the
start of a bus request.
During the second cycle of the issue phase, this signal is the MSB
of a value which indicates the length of the transaction.
BE[7:0]#
8
O
Rst(Z)
Hld(Q)
1
Slp(Z)
Byte Enable
: Signifies which bytes are valid during a write
transaction. When not in use, this bus is floated (Z).
CLK
1
I
CLK
: Clock input for the core logic.
CWF/
DBusWidth
(Config. Pin)
1
I
Critical Word First
: When active during a data read transaction,
CWF
informs the core of the data wrap order.
DBusWidth
: While
RESET#
is asserted, this pin is sampled by the
Intel
80200 processor to determine when the data bus is to be
configured as 32-bits or 64-bits. When the pin is sampled as
‘
0
’
during reset, the 80200 assumes a 64-bit bus. When the pin is
‘
1
’
at
reset, a 32-bit bus is assumed.
D[63:0]
64
I/O
Rst(Z)
Hld(Q)
1
Slp(Z)
Data Bus
: Carries data to/from the processor during a bus
transaction. When not in use, this bus is floated (Z).
DCB[7:0]
8
I/O
Rst(Z)
Hld(Q)
1
Slp(Z)
Data Check Byte
: Carries the optional ECC information associated
with the data on the Data bus. When not in use, this bus is floated
(Z).
DVALID
1
I
Data Valid
: Asserted when
the Data bus
carries valid data.
FIQ#
1
I
Fast Interrupt Request
: When FIQs are enabled, the processor
responds to a low level on this input by taking the FIQ interrupt
exception.
HLDA
1
O
Rst(0)
Hld(1)
Slp(0)
HLDA
: This output is asserted when the 80200 has floated the
shared bus signals in response to
HOLD
.
相關PDF資料 |
PDF描述 |
|---|---|
| FW802C | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW802C-DB | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW803-09-DB | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW803 | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW804-09-DB | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FW802B | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE㈢ 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802B-DB | 制造商:Legerity 功能描述:DUAL LINE TRANSCEIVER, PQFP64 |
| FW802BF | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device |
| FW802BF-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device |
| FW802C | 制造商:AGERE 制造商全稱:AGERE 功能描述:FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
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