- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370260 > FW802C-DB FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE PDF資料下載
參數(shù)資料
| 型號： | FW802C-DB |
| 英文描述： | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| 中文描述： | 防火墻802C低-動力IEEE 1394A端口- 2000兩艘電纜收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 301K |
| 代理商： | FW802C-DB |
18
Agere Systems Inc.
Data Sheet, Rev. 1
October 2002
Two-Cable Transceiver/Arbiter Device
FW802C Low-Power PHY IEEE1394A-2000
Internal Register Configuration
The PHY register map is shown below in Table 8.
Table 8. PHY Register Map for the Cable Environment
The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values
not specified are resolved by the operation of the PHY state machines subsequent to a power reset.
Table 9. PHY Register Fields for the Cable Environment
Address
Contents
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0000
2
Physical_ID
R
PS
0001
2
RHB
IBR
Gap_count
0010
2
Extended (7)
XXXXX
XXXXX
Jitter
Total_ports
0011
2
Max_speed
Delay
0100
2
LCtrl
Contender
Pwr_class
0101
2
Resume_int
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Page_select
XXXXX
Register 0
Page_select
ISBR
Loop
Pwr_fail
Timeout
Port_event Enab_accel Enab_multi
0110
2
XXXXX
0111
2
Port_select
1000
2
1111
2
Register 7
Page_select
REQUIRED
XXXXX
RESERVED
Field
Size Type
Power Reset
Value
Description
Physical_ID
6
r
000000
The address of this node determined during self-identification. A
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
When set to one, indicates that this node is the root.
Cable power active.
Root hold-off bit. When set to one, the force_root variable is TRUE,
which instructs the PHY to attempt to become the root during the
next tree identify process.
Initiate bus reset. When set to one, instructs the PHY to set ibr
TRUE and reset_time to RESET_TIME. These values, in turn,
cause the PHY to initiate a bus reset without arbitration; the reset
signal is asserted for 166
μ
s. This bit is self-clearing.
Used to configure the arbitration timer setting in order to optimize
gap times according to the topology of the bus. See Section 4.3.6
of
IEEE
Standard
1394
-1995 for the encoding of this field.
This field has a constant value of seven, which indicates the
extended PHY register map.
R
PS
RHB
1
1
1
r
r
0
—
0
rw
IBR
1
rw
0
Gap_count
6
rw
3F
16
Extended
3
r
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW803-09-DB | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW803 | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW804-09-DB | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
| FW804 | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
| FW80960RP-33 | I/O Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW803 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW803-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW80321M400 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80321 I/O Processor |
| FW80321M400SL6R2 | 功能描述:IC I/O PROCESSOR CMOS 544BGA PKG RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| FW80321M600SL6R3 | 功能描述:IC MPU 32-BIT PCI XSCALE 544BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復。