參數(shù)資料
型號(hào)： FW802C-DB
英文描述： FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
中文描述： 防火墻802C低-動(dòng)力IEEE 1394A端口- 2000兩艘電纜收發(fā)器/仲裁器裝置
文件頁數(shù)： 2/24頁
文件大小： 301K
代理商： FW802C-DB
2
Agere Systems Inc.
Data Sheet, Rev. 1
October 2002
Two-Cable Transceiver/Arbiter Device
FW802C Low-Power PHY IEEE1394A-2000
Table of Contents
Contents
Page
Distinguishing Features ............................................................................................................................................1
Features ...................................................................................................................................................................1
Other Features .........................................................................................................................................................1
Description ................................................................................................................................................................3
Signal Information .....................................................................................................................................................6
Application Information ...........................................................................................................................................10
1394Application Support Contact Information .......................................................................................................11
Crystal Selection Considerations ............................................................................................................................11
Load Capacitance ............................................................................................................................................12
Board Layout ....................................................................................................................................................12
Absolute Maximum Ratings ....................................................................................................................................12
Electrical Characteristics ........................................................................................................................................13
Timing Characteristics ............................................................................................................................................16
Timing Waveforms ..................................................................................................................................................17
Internal Register Configuration ...............................................................................................................................18
Outline Diagrams ....................................................................................................................................................23
48-Pin TQFP ....................................................................................................................................................23
Ordering Information ...............................................................................................................................................23
List of Figures
Figures
Page
Figure 1. Block Diagram ........................................................................................................................................5
Figure 2. Pin Assignments .....................................................................................................................................6
Figure 3. Typical External Component Connections ...........................................................................................10
Figure 4. Typical Port Termination Network ........................................................................................................11
Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ..........................................................17
Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms ....................................................................17
List of Tables
Tables
Page
Table 1. Signal Descriptions...................................................................................................................................7
Table 2. Absolute Maximum Ratings....................................................................................................................12
Table 3. Analog Characteristics............................................................................................................................13
Table 4. Driver Characteristics.............................................................................................................................14
Table 5. Device Characteristics............................................................................................................................15
Table 6. Switching Characteristics .......................................................................................................................16
Table 7. Clock Characteristics .............................................................................................................................16
Table 8. PHY Register Map for the Cable Environment ......................................................................................18
Table 9. PHY Register Fields for the Cable Environment ....................................................................................18
Table 10. PHY Register Page 0: Port Status Page .............................................................................................20
Table 11. PHY Register Port Status Page Fields ................................................................................................21
Table 12. PHY Register Page 1: Vendor Identification Page ..............................................................................22
Table 13. PHY Register Vendor Identification Page Fields .................................................................................22
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