參數(shù)資料
型號： FW802C-DB
英文描述： FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
中文描述： 防火墻802C低-動力IEEE 1394A端口- 2000兩艘電纜收發(fā)器/仲裁器裝置
文件頁數(shù)： 19/24頁
文件大?。?/td> 301K
代理商： FW802C-DB
Agere Systems Inc.
19
Data Sheet, Rev. 1
October 2002
Two-Cable Transceiver/Arbiter Device
FW802C Low-Power PHY IEEE1394A-2000
Internal Register Configuration
(continued)
Table 9. PHY Register Fields for the Cable Environment
(continued)
Field
Size Type Power Reset Value
Description
Total_ports
4
r
2
The number of ports implemented by this PHY. This count
reflects the number.
Indicates the speed(s) this PHY supports:
000
2
= 98.304 Mbits/s
001
2
= 98.304 and 196.608 Mbits/s
010
2
= 98.304, 196.608, and 393.216 Mbits/s
011
2
= 98.304, 196.608, 393.216, and 786.43 Mbits/s
100
2
= 98.304, 196.608, 393.216, 786.432, and
1,572.864 Mbits/s
101
2
= 98.304, 196.608, 393.216, 786.432, 1,572.864, and
3,145.728 Mbits/s
All other values are reserved for future definition.
Worst-case repeater delay, expressed as 144 + (delay * 20) ns.
Link Active.
Cleared or set by software to control the value of
the L bit transmitted in the node’s self-ID packet 0, which will be
the logical AND of this bit and LPS active.
Cleared or set by software to control the value of the C bit
transmitted in the self-ID packet. Powerup reset value is set by
C/LKON pin.
The difference between the fastest and slowest repeater data
delay, expressed as (jitter + 1) * 20 ns.
Power Class.
Controls the value of the pwr field transmitted in
the self-ID packet. See Section 4.3.4.1 of
IEEE
Standard
1394
-
1995 for the encoding of this field.
Resume Interrupt Enable.
When set to one, the PHY will set
Port_event to one if resume operations commence for any port.
Initiate Short (Arbitrated) Bus Reset.
A write of one to this bit
instructs the PHY to set ISBR true and reset_time to
SHORT_RESET_TIME. These values, in turn, cause the PHY
to arbitrate and issue a short bus reset. This bit is self-clearing.
Loop Detect.
A write of one to this bit clears it to zero.
Cable Power Failure Detect.
Set to one when the PS bit
changes from one to zero. A write of one to this bit clears it to
zero.
Arbitration State Machine Time-out.
A write of one to this bit
clears it to zero (see MAX_ARB_STATE_TIME).
Port Event Detect.
The PHY sets this bit to one if any of con-
nected, bias, disabled, or fault change for a port whose
Int_enable bit is one. The PHY also sets this bit to one if
resume operations commence for any port and Resume_int is
one. A write of one to this bit clears it to zero.
Max_speed
3
r
010
2
Delay
LCtrl
4
1
r
0000
1
rw
Contender
1
rw
See description.
Jitter
3
r
000
Pwr_class
3
rw
See description.
Resume_int
1
rw
0
ISBR
1
rw
0
Loop
Pwr_fail
1
1
rw
rw
0
1
Timeout
1
rw
0
Port_event
1
rw
0
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