參數(shù)資料
型號(hào)： GS8171DW72AGC-250
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 256K X 72 STANDARD SRAM, 2.1 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁(yè)數(shù)： 4/33頁(yè)
文件大小： 1041K
代理商： GS8171DW72AGC-250
GS8171DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
12/33
2003, GSI Technology
.
HSTL Output Driver Impedance Control
HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an
external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value
of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-
specified tolerance is between 150
and 300. Periodic readjustment of the output driver impedance is necessary as the
impedance is affected by drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance
evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time
towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates
for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z. The
SRAM requires 32K start-up cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output
driver impedance.
Pipelined Read Bank Switch with E1 Deselect
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD
QC
CQ
Bank 1
CQ1 + CQ2
CQ
Bank 2
DQ
Bank 2
QA
Address
A
XX
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
F
DE
C
Read
CK
Read
No Op
相關(guān)PDF資料
PDF描述
GS8171DW72AGC-350IT 256K X 72 STANDARD SRAM, 1.7 ns, PBGA209
GS820H32GT-138I 64K X 32 CACHE SRAM, 9.7 ns, PQFP100
GS820H32GT-5I 64K X 32 CACHE SRAM, 12 ns, PQFP100
GS832032AGT-200 CACHE SRAM, PQFP100
GS8320V32GT-166IT 1M X 32 CACHE SRAM, 8 ns, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8171DW72AGC-300 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays
GS8171DW72AGC-333 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays
GS8171DW72AGC-350 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays
GS8171DW72AGC-350I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays
GS8180Q36D-167X 制造商:GSI Technology 功能描述:512K X 36 (18 MEG)SIGMA QUAD I -SEPERATE I/O BURST OF 2 - Trays
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