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參數(shù)資料
| 型號： | GS8171DW72AGC-350IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 72 STANDARD SRAM, 1.7 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209 |
| 文件頁數(shù)： | 2/33頁 |
| 文件大?。?/td> | 1041K |
| 代理商： | GS8171DW72AGC-350IT |
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GS8171DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
10/33
2003, GSI Technology
Programmable Enables
ΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at VDD,
E2 functions as an active high enable. If EP2 is held to VSS, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
SRAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic—
Σ1x1Dp
A
CK
E1
E2
E3
W
A0–An
CK
W
DQ0–DQn
Bank 0
Bank 1
Bank 2
Bank 3
Bank Enable Truth Table
EP2
EP3
E2
E3
Bank 0
VSS
Active Low
Bank 1
VSS
VDD
Active Low
Active High
Bank 2
VDD
VSS
Active High
Active Low
Bank 3
VDD
Active High
E1
An – 1
An
A0–An – 2
An – 1
An
A0–An – 2
An – 1
An
A0–An – 2
An – 1
An
A0–An – 2
DQ
A
CK
E2
E3
W
DQ
A
CK
E2
E3
W
DQ
A
CK
E2
E3
W
DQ
E1
CQ
EP2
EP3
0
EP2
EP3
1
0
EP2
EP3
0
1
EP2
EP3
1
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