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參數(shù)資料
| 型號： | GS832236E-225IV |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 CACHE SRAM, 7 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大小： | 1537K |
| 代理商： | GS832236E-225IV |
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GS832218/36/72(B/E/C)-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06a 12/2007
31/42
2003, GSI Technology
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS832236GB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS832236GB-200E | 制造商:GSI Technology 功能描述:GS832236GB-200E - Trays |
| GS832236GB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS832236GB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS832236GB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
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