參數(shù)資料
型號(hào)： GS8324Z72GC-133IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 72 ZBT SRAM, 10 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁(yè)數(shù)： 15/46頁(yè)
文件大?。?/td> 1157K
代理商： GS8324Z72GC-133IT
Rev: 1.00 10/2001
22/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
x18/x36 Mode (PE = 1) Write Parity Error Output Timing Diagram
BPR 1999.05.18
Burst Counter Sequences
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
CK
D In A
D In B
D In C
D In D
D In E
tKQ
tHZ
tKQX
tLZ
DQ
QE
Fl
ow
Th
ro
ug
h
M
od
e
Pi
pe
lin
ed
M
od
e
tKQ
tHZ
tKQX
tLZ
DQ
QE
D In A
D In B
D In C
D In D
D In E
Err A
Err C
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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