參數(shù)資料
型號： GS8324Z72GC-133IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 72 ZBT SRAM, 10 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù)： 35/46頁
文件大?。?/td> 1157K
代理商： GS8324Z72GC-133IT
Rev: 1.00 10/2001
40/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Notes:
1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,
PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.
2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.
3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control
is effective after JTAG EXTEST instruction is executed.
4. 1 = no connect, internally set to logic value 1
5. 0 = no connect, internally set to logic value 0
6. X = no connect, value is undefined
GS8324Z18/36/72 Boundary Scan Chain Order
Order
x72
x36
x18
Bump
x72
x36 x18
1(TBD)
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