參數(shù)資料
型號(hào)： HC05JB3GRS
英文描述： 68HC05JB3 and 68HC705JB3 General Release Specification
中文描述： 68HC05JB3和68HC705JB3總發(fā)行規(guī)格
文件頁數(shù)： 12/106頁
文件大?。?/td> 1366K
代理商： HC05JB3GRS
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
1-2
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MC68HC05J5A
REV 2.1
14 Bidirectional I/O pins (10 I/O pins on 16-pin package)
– PA0-PA5, PB0, and PB3-PB5: with software programmable input pull-
down devices
– PB1, PB2, PA6 and PA7: open-drained I/O pins with software
programmable pull-up devices
– PA6, PA7, and PB1: with slow output falling transition feature
– PA7: with falling-edge interrupt capability
– PA0-PA3: with maskable rising-edge only or rising-edge and high
level interrupt capability
– 20-pin package: PB1 and PB2, each with 25mA current sink
capability
– 16-pin package: PB1 with 50mA current sink capability
Computer Operation Properly (COP) Watchdog
Low Voltage Reset Circuit
Illegal Address Reset
20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages
1.2
MASK OPTIONS
The following mask options are available on the MC68HC05J5A:
1.3
MCU STRUCTURE
Figure 1-1
shows the structure of MC68HC05J5A MCU.
MASK
OPTION
STOP instruction convert to WAIT
[Enabled] or [Disabled]
External interrupt pins (IRQ, PA0-PA3)
[Edge-triggered] or [Edge and level triggered]
Port A and Port B pull-down/pull-up resistors
[Enabled] or [Disabled]
PA0-PA3 external interrupt capability
[Enabled] or [Disabled]
Oscillator Delay Option (internal clock cycles)
[224] or [4064]
Low Voltage Reset
[Enabled] or [Disabled]
COP Watchdog Timer
[Enabled] or [Disabled]
F
Freescale Semiconductor, Inc.
n
.
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