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| 型號： | HC05JB3GRS |
| 英文描述： | 68HC05JB3 and 68HC705JB3 General Release Specification |
| 中文描述： | 68HC05JB3和68HC705JB3總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 65/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05JB3GRS |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
16-BIT TIMER
MOTOROLA
9-7
Figure 9-9. TCAP Input Comparator Output
When the input capture circuitry detects an active edge on the TCAP pin, it
latches the contents of the free-running timer counter registers into the input cap-
ture registers as shown in
Figure 9-6
.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter val-
ues at successive edges of opposite polarity measures the pulse width of the sig-
nal.
The input capture registers are made up of two 8-bit read-only registers (ICH, ICL)
as shown in
Figure 9-10
. The input capture edge detector contains a Schmitt trig-
ger to improve noise immunity. The edge that triggers the counter transfer is
defined by the input edge bit (IEDG) in the T1CR. Reset does not affect the con-
tents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
BIT 7
Bit15
BIT 6
Bit14
BIT 5
Bit13
BIT 4
Bit12
BIT 3
Bit11
BIT 2
Bit10
BIT 1
Bit9
BIT 0
Bit8
ICH
$0014
R
W
reset:
U
U
U
U
U
U
U
U
ICL
$0015
R
W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
reset:
U
U
U
U
U
U
U
U
U = UNAFFECTED BY RESET
Figure 9-10. Input Capture Registers (ICH, ICL)
V
DD
÷ 2
V
DD
Output of Comparator
Signal on TCAP pin
Time
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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