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| 型號(hào)： | HC05JB3GRS |
| 英文描述： | 68HC05JB3 and 68HC705JB3 General Release Specification |
| 中文描述： | 68HC05JB3和68HC705JB3總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 27/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05JB3GRS |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
INTERRUPTS
MOTOROLA
4-1
SECTION 4
INTERRUPTS
The MCU can be interrupted in six different ways:
Non-maskable Software Interrupt Instruction (SWI)
External Asynchronous Interrupt (IRQ)
Optional External Interrupt via IRQ on PA0-PA3 (by a mask option)
External Interrupt via IRQ on PA7
Multi-Function Timer (MFT)
16-Bit Timer Interrupt (Timer1)
4.1
CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware
interrupts do not cause the current instruction execution to be halted, but are con-
sidered pending until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding inter-
rupt enable bit is set the processor will proceed with interrupt processing. Other-
wise, the next instruction is fetched and executed. If an interrupt occurs the
processor completes the current instruction, then stacks the current CPU register
states, sets the I-bit to inhibit further interrupts, and finally checks the pending
hardware interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in
Table 4-1
will be
serviced first. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the appro-
priate interrupt software service routine from the vector table at locations $0FF6
thru $0FFF as defined in
Table 4-1
.
Table 4-1. Vector Address for Interrupts and Reset
N/A
N/A
IRQF/IRQF1
TOF
RTIF
T1OF, ICF
Register
N/A
N/A
ICSR
TCSR
TCSR
T1SR
Flag
Name
Interrupts
Reset
Software
External Interrupt
MFT Overflow
Real Time Interrupt
Timer1 Interrupt
CPU
Interrupt
RESET
SWI
IRQ
MFT
MFT
TIMER1
Vector Address
$0FFE-$0FFF
$0FFC-$0FFD
$0FFA-$0FFB
$0FF8-$0FF9
$0FF8-$0FF9
$0FF6-$0FF7
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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