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參數(shù)資料
| 型號： | HD49334A |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | CDS/PGA & 10-bit A/D Converter |
| 中文描述： | 的CDS /美國PGA |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 242K |
| 代理商： | HD49334A |
HD49334AF/AHF
Rev.1.0, Apr 20, 2004, page 10 of 22
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
0
1
2
9
10
11
N+1
N+2
N+9
N+10
N+11
N
N
9
N
8
N
1
N
CDSIN
SPBLK
SPSIG
ADCLK
D0 to D9
N+2
N+8
N+9
N+10
N+11
N
8
N
9
N
1
ADCIN
ADCLK
D0 to D9
N
N+1
N
N+1
N
10
When CDSIN input mode is used
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
When ADCIN input mode is used
~
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.
In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD49334AF | CDS/PGA & 10-bit A/D Converter |
| HD49335F | CDS/PGA AND 10-bit A/D TG Converter |
| HD49335HF | CDS/PGA AND 10-bit A/D TG Converter |
| HD49338F | CDS/PGA & 12-bit A/D Converter |
| HD49338HF | CDS/PGA & 12-bit A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD49334AF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49334AHNP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49334ANP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49335F | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter |
| HD49335HF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter |
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