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參數(shù)資料
| 型號： | HD49334A |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | CDS/PGA & 10-bit A/D Converter |
| 中文描述： | 的CDS /美國PGA |
| 文件頁數(shù)： | 15/23頁 |
| 文件大小： | 242K |
| 代理商： | HD49334A |
HD49334AF/AHF
Rev.1.0, Apr 20, 2004, page 15 of 22
Clamp (D3 to D7 of register 2)
Determine the OB part level with digital code of ADC output.
Clamp level = setting data
×
2 + 14
Default data is 9 = 32 LSB.
HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.
Low_PWR (D12 of register 2)
Switch circuit current and frequency characteristic.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
SPinv (D13 of register 2)
SPSIG/SPBLK/PBLK input signal inverted switching.
Data = 1: Normal
Data = 0: Inverted
Reset (D15 of register 2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be done when starting up with using this bit. Details are referred to page 19.
C_Bias_off (D3 of register 3)
Center bias is turned off in ADCIN mode.
Data = 0: Normally on
Data = 1: Off
Ave_4H (D6 of register 3)
Clamp detection data is averaged 4H.
Data = 0: 1H
Data = 1: Averaged 4H
Differential Code and Gray Code
(D4 to D5 and D7 to D9 of register 3)
Gray code (D4 to D5 of register 3)
DC output code can be change to following type.
Gray Code [1]
Gray Code [0]
0
0
0
1
1
0
1
1
Serial data setting items (D7 to D9 of register 3)
Setting Bit
Setting Contents
Gray_test[0]
Gray_test[1]
(Refer to the following table)
Gray_test[2]
ADCLK polar with OBP. (Lo
→
Positive edge, HI
→
Negative edge)
Standard data output timing
Gray_test[1]
Gray_test[0]
Low
Low
Low
High
High
Low
High
High
Output Code
Binary code
Gray code
Differential encoded binary
Differential encoded gray
Standard data output timing control signal
Standard Data Output Timing
Third and fourth
Fourth and fifth
Fifth and sixth
Sixth and seventh
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD49334AF | CDS/PGA & 10-bit A/D Converter |
| HD49335F | CDS/PGA AND 10-bit A/D TG Converter |
| HD49335HF | CDS/PGA AND 10-bit A/D TG Converter |
| HD49338F | CDS/PGA & 12-bit A/D Converter |
| HD49338HF | CDS/PGA & 12-bit A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD49334AF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49334AHNP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49334ANP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49335F | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter |
| HD49335HF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter |
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