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參數(shù)資料
| 型號(hào)： | HD49334A |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | CDS/PGA & 10-bit A/D Converter |
| 中文描述： | 的CDS /美國(guó)PGA |
| 文件頁(yè)數(shù)： | 11/23頁(yè) |
| 文件大?。?/td> | 242K |
| 代理商： | HD49334A |
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HD49334AF/AHF
Rev.1.0, Apr 20, 2004, page 11 of 22
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
Note:
Black
level
Signal
level
D0 to D9
1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities
of the SPBLK and the SPSIG are inverted.)
CDSIN
SPBLK
Vth
(2)
(3)
SPSIG
ADCLK
(7)
Vth
Vth
(8)
(9)
(10)
(4)
(1)
(5)
(6)
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8
Timing Specifications when the CDSIN Input Mode is Used
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7), (8) ADCLK t
WH
min./t
WL
min.
(9)
ADCLK rising to digital output hold time
(10)
ADCLK rising to digital output delay time
Note: 1. SPBLK and SPSIG polarities when serial data Spinv bit is set to low.
Timing
Black-level signal fetch time
SPBLK low period *
1
Signal-level fetch time
SPSIG low period *
1
SPBLK rising to SPSIG rising time *
1
SPSIG rising to ADCLK rising inhibition time *
1
Symbol
t
CDS1
t
CDS2
t
CDS3
t
CDS4
t
CDS5
t
CDS6
t
CDS7, 8
t
CHLD9
t
COD10
Min
—
Typ
×
0.8
—
Typ
×
0.8
Typ
×
0.85
1
11
3
—
Typ
(1.5)
1/4f
CLK
(1.5)
1/4f
CLK
1/2f
CLK
5
—
7
16
Max
—
Typ
×
1.2
—
Typ
×
1.2
Typ
×
1.15
11
—
—
24
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is input. The average of the black signal
level is taken for eight input cycles during the OB period and becomes the clamp level (DC standard).
CDSIN
OBP
Note:
OB pulse > 2 clock cycles
When serial data OBPinv bit is set to low
(When the OBPinv is set to high, the polarity of the OBP is inverted.)
OB period *
1
1. Shifts
±
1 clock cycle depending on the OBP input timing.
N
N+1
N+5
N+12
N+13
This edge is used, when OBP pulse-width period is clamp-on.
Figure 4 OBP Detailed Timing Specifications
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD49334AF | CDS/PGA & 10-bit A/D Converter |
| HD49335F | CDS/PGA AND 10-bit A/D TG Converter |
| HD49335HF | CDS/PGA AND 10-bit A/D TG Converter |
| HD49338F | CDS/PGA & 12-bit A/D Converter |
| HD49338HF | CDS/PGA & 12-bit A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD49334AF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49334AHNP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49334ANP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49335F | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter |
| HD49335HF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter |
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