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Rev. 2.0, 09/99, page x of xiii
Table 13-6. ECP Mode Description ........................................................................................ 157
Table 13-7. Device Status Register Description....................................................................... 158
Table 13-8. Device Control Register Description .................................................................... 158
Table 13-9. Configuration Register B Description................................................................... 159
Table 13-10. ECR Register Description .................................................................................. 159
Table 14-1. Pin Function of Serial CODEC Interface Module ................................................. 163
Table 14-2. Registers of SCDI ................................................................................................ 163
Table 14-3. AC97 Timing....................................................................................................... 207
Table 15-1. Pin Function of AFE Interface Module ................................................................. 211
Table 15-2. Registers of AFE Interface ................................................................................... 212
Table 16-1. Pin Function of Keyboard Controller Interface Module......................................... 226
Table 16-2. Keyboard Controller Interface Read Cycle AC Timing ......................................... 229
Table 16-3. Keyboard Controller Interface Write Cycle AC Timing ........................................ 229
Table 17-1. The Register List of USB Device Controller......................................................... 232
Table 17-2. SIE Handshake Control Table .............................................................................. 237
Table 17-3. FIFO Depth of Endpoint ...................................................................................... 238
Table 17-4. Interrupt Priority Level ........................................................................................ 248
Table 17-5. The Table for Transmit Ready.............................................................................. 252
Table 17-6. Truth Table for TX Endpoint Transmit Enable Status ........................................... 253
Table 17-7. The Table for the Handshake Returns to Host after Token Phase........................... 253
Table 17-8. The Table for Receive Ready ............................................................................... 255
Table 17-9. Truth Table for RX Endpoint Reception Enable Status ......................................... 255
Table 17-10. The Table for the Handshake Returns to Host after Token Phase......................... 256
Table 18-1. A/D Converter Pins.............................................................................................. 260
Table 18-2. A/D Converter Registers ...................................................................................... 261
Table 18-3. Analog Input Channels and A/D Data Registers.................................................... 262
Table 18-4. A/D Conversion Time (Single Mode) ................................................................... 270
Table 18-5. A/D Conversion Characteristics ........................................................................... 271
Table 18-6. Analog Input Pin Characteristics .......................................................................... 272
Table 19-1. LCD Mode .......................................................................................................... 273
Table 19-2. CRT Mode........................................................................................................... 274
Table 19-3. Definition of Supported Raster-Operation ............................................................ 275
Table 19-4. Results of BitBLT Raster-Operation..................................................................... 276
Table 21-1. CPU Interface AC Timing Spec. ......................................................................... 321
Table 21-2. GPIO AC Timing Spec. ...................................................................................... 321
Table 21-3. I/O Port Interrupt AC Timing Spec. ..................................................................... 322
Table 21-4. PCMCIA AC Timing Spec. ................................................................................. 322
Table 21-5. UART AC Timing Spec. ..................................................................................... 322
Table 21-6. Parallel Port AC Timing Spec. ............................................................................ 323
Table 21-7. SCDI AC Timing Spec. ....................................................................................... 323
Table 21-8. AFE Interface AC Timing Spec. .......................................................................... 324
Table 21-9. KBC AC Timing Spec. ....................................................................................... 324
Table 21-10. EDO-RAM Access AC Timing Spec. – Read Cycle*.......................................... 325