參數(shù)資料
型號: HD66841
廠商: Hitachi,Ltd.
英文描述: LVIC-II (LCD Video Interface Controller)(LCD視頻控制器)
中文描述: LVIC - 2(液晶視頻接口控制器)(液晶顯示視頻控制器)
文件頁數(shù): 26/62頁
文件大?。?/td> 185K
代理商: HD66841
HD66841
26
Dot Clock Generation
The dot clock, which is a data latch clock, is not a standard video signal, so it is not usually output from the
CRT display plug. Therefore, the HD66841 must generate it. The HD66841 has a programmable counter
and a phase comparator which are parts of a phase-locked loop (PLL) circuit, and it can generate the dot
clock from the HSYNC signal if a charge pump, a low-pass filter (LPF), and a voltage-controlled oscillator
(VCO) are externally attached.
A block diagram of the PLL circuit is shown in Figure 11. A PLL circuit is a feedback controller that
generates a clock whose frequency and phase are the same as those of a basic clock. The basic clock is the
HSYNC signal in this case.
At power-on, the VCO outputs to the programmable counter a signal whose frequency is determined by the
voltage at the time. The counter divides the frequency of the signal according to the value in the PLL
frequency-dividing ratio register (R10, R11) and outputs it to the phase comparator. This is the frequency-
divided clock.
The comparator compares the edges of the clock pulses and the HSYNC signal pulses and output the
CU
or
CD
signal to the charge pump and LPF according to the result. The comparator outputs the
CU
signal if the
frequency of the clock is lower than that of the HSYNC signal or if the phase of the clock is behind that of
the HSYNC, signal; otherwise it outputs the
CD
signal. The charge pump and LPF apply a voltage to the
VCO according to the
CU
or
CD
signal.
This operation is repeated until the phase and frequency of the frequency-divided clock match those of the
HSYNC signal, making it a stable dot clock.
HSYNC
Phase
comparator
Frequency-
divided clock
Programmable
counter
DOTCLK
Timing clock generator
Written value in PLL
frequency-dividing ratio
register (R10, R11)
Inside HD66841
Charge pump
LPF
VCO
CU
CD
Figure 11 PLL Circuit Block Diagram
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