參數(shù)資料
型號(hào)： HD66841
廠商： Hitachi,Ltd.
英文描述： LVIC-II (LCD Video Interface Controller)(LCD視頻控制器)
中文描述： LVIC - 2（液晶視頻接口控制器）（液晶顯示視頻控制器）
文件頁(yè)數(shù)： 40/62頁(yè)
文件大?。?/td> 185K
代理商： HD66841
HD66841
40
10. Vertical Backporch Register (R12, R13)
The 8-bit vertical backporch register (Figure 28) specifies the vertical backporch which is the number of
lines between the active edge of the vertical synchronization signal (VSYNC) and the rising edge of the
display timing signal (DISPTMG), if the DISPTMG signal is generated internally. For details on the
vertical backporch, refer to the Display Timing Signal Generation section and Figure 10.
This register is invalid if the DISPTMG signal is supplied externally. It is valid only in the internal register
programming method when the DSP bit of control register 1 (R0) is 1. However, note that if the DCK bit of
control register 1 (R0) is 1, the DISPTMG signal will always be regenerated internally so this register is
enabled even if the DSP bit of control register 1 (R0) is 0.
11. Horizontal Backporch Register (R14, R15)
The 8-bit horizontal backporch register (Figure 29) specifies the horizontal backporch which is the number
of dots between the rising edge of the HSYNC signal and that of the display timing signal (DISPTMG), if
the DISPTMG signal is generated internally. For details on the horizontal backporch, refer to Display
Timing Signal Generations section and Figure 10.
This register is invalid if the DISPTMG signal is supplied externally. It is valid only in the internal register
programming method when the DSP bit of control register 1 (R0) is 1. However, note that if the DCK bit of
control register 1 (R0) is 1, the DISPTMG signal will always be generated internally so this register is
enabled even if the DSP bit of control register 1 (R0) is 0.
Data bit
Value
3
2
1
0
3
2
1
0
R12
(Unit: Lines)
Ncvbp – 1
Ncvbp: Vertical backporch = number of lines between the active edge of the VSYNC signal and
the rising edge of the DISPTMG signal (the SPS pin must be set high if the VSYNC signal
is active-high or low if it is active-low)
R13
Figure 28 Vertical Backporch Register
Data bit
Value
3
2
1
0
3
2
1
0
R14
R15
Nchbp – 1
Nchbp:
(Unit: Dots)
Horizontal backportch = number of dots between the rising edge of the HSYNC signal
(just before the rising edge of the DISPTMG signal) and the rising edge of the DISPTMG
signal
Figure 29 Horizontal Backporch Register
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