參數(shù)資料
型號(hào)： HD66841
廠商： Hitachi,Ltd.
英文描述： LVIC-II (LCD Video Interface Controller)(LCD視頻控制器)
中文描述： LVIC - 2（液晶視頻接口控制器）（液晶顯示視頻控制器）
文件頁(yè)數(shù)： 36/62頁(yè)
文件大小： 185K
代理商： HD66841
HD66841
36
4. Vertical Displayed Lines Register (R2, R3, High-Order 2 Bits of R4)
The vertical displayed lines register (Figure 22) is composed of ten bits (R2, R3, and the high-order two
bits of R4). It specifies the number of lines displayed from top to bottom of the screen, called the number of
vertical displayed lines. This register can specify both even and odd numbers in single screen modes with
Y-drivers positioned on one side, i.e., in display modes 2, 4, and 7-9, but can specify only even numbers in
other modes. The value to be written into this register is Nvd – 1, where Nvd is the number of vertical
displayed lines.
5. CL3 Period Register (Low-Order 2 Bits of R4, R5)
The CL3 period register (Figure 22), is composed of six bits (R5 and the low-order two bits of R4). It
specifies the CL3 signal period in 8-color display modes with horizontal stripes (display modes 13–15), so
it is invalid in other modes. CL3 is the clock signal used by the HD66841 to output RGB data separately to
LCD drivers. The value to be written into this register is Npc – 1, i.e., (Nhd + 6)
×
1/3 – 1, where Nhd is the
number of horizontal displayed dots
×
1/8. If (Nhd + 6) is not divisible by 3, rounded it off.
3
2
3
2
1
0
3
2
1
0
1
0
3
2
1
0
Data bit
Value
R5
R4
R3
R2
R4
Nvd – 1 (Unit: Lines)
(Nhd + 6)
×
1/3 – 1
(Unit: Characters)
Vertical displayed lines register
CL3 period register
Nvd:
Npc:
Nhd:
Number of vertical displayed lines
CL3 period = (Nhd + 6)
×
1/3
Number of horizontal displayed characters
(number of horizontal displayed dots
×
1/8)
Figure 22 Vertical Displayed Lines Register and CL3 Period Register
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