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參數(shù)資料
| 型號(hào)： | HD66841 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | LVIC-II (LCD Video Interface Controller)(LCD視頻控制器) |
| 中文描述： | LVIC - 2（液晶視頻接口控制器）（液晶顯示視頻控制器） |
| 文件頁(yè)數(shù)： | 31/62頁(yè) |
| 文件大?。?/td> | 185K |
| 代理商： | HD66841 |
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HD66841
31
Display Timing Signal Fine Adjustment
If the display timing signal is supplied externally, a phase shift between CRT data and the display timing
signal may appear. This is because each signal has its own specific lag. The HD66841 can adjust the
display timing signal according to pins F0–F3 or the fine adjust register (R9) to correct the phase shift.
The relationships between pins F3–F0, data bits 3 to 0 of the fine adjust register, and the resultant fine
adjustments are shown in Table 13. The polarity of the number of dots adjusted is given by – (minus)
indicates advancing the phase of the display timing signal or + (plus) indicating delaying it. Pin F3 or data
bit 3 of R9 selects the polarity. The adjustment reference point is the display start position.
Examples of adjusting the display timing signal are shown in Figure 17. Since the signal is two dots ahead
of the display start position in case (1), F3, F2, F1, and F0 or data bits 3, 2, 1, and 0 of R9 should be set to
(1, 0, 1, 0) to delay the signal by two dots. Conversely, since the signal is two dots behind the display start
position in case (2), they should be set to (0, 0, 1, 0) to advance the signal by two dots. If there is no need to
adjust the signal, a settings of either (0, 0, 0, 0) or (1, 0, 0, 0) will do.
Table 13
Pins, Data Bits of R9, and Fine Adjustment
Pin:
F3
F2
F1
F0
Number of Dots
Adjusted
R9 Bit:
3
2
1
0
0
0
0
0
0
0
.
.
.
0
.
.
.
1
.
.
.
–1
.
.
.
1
1
0
–6
1
1
1
–7
1
0
0
0
0
0
.
.
.
0
.
.
.
1
.
.
.
+1
.
.
.
1
1
0
+6
1
1
1
+7
Note:
To use pins to adjust the display timing signal, set the ADJ pin to 1.
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相關(guān)代理商/技術(shù)參數(shù) |
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