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參數(shù)資料
| 型號： | HI3197 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 125 MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.0035 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 284K |
| 代理商： | HI3197 |
16
FIGURE 8A.
FIGURE 8B. EXAMPLE WHEN NOT USING THE RESET SIGNAL
FIGURE 8C. EXAMPLE WHEN USING THE RESET SIGNAL
FIGURE 8. MUX.1B MODE
HI3197 (MUX. 1B MODE)
CLOCK INPUT PIN
RESET INPUT PIN
DA0 TO DA9
DB0 TO DB9
1/2
CLOCK
RESET SIGNAL
(WHEN ACTIVE LOW)
INTERNALLY 1/2
FREQUENCY-DIVIDED SIGNAL
(THIS SIGNAL CANNOT BE OBSERVED)
t
S
t
H
t
H-RST
t
S-RST
AFTER THE RESET IS RELEASED, THE INTERNAL 1/2 FREQUENCY-DIVIDED SIGNAL COMMENCES AT THE FIRST CLOCK EDGE, SO BE SURE TO INPUT
THE DATA IN A MANNER THAT SATISFIES THE SETUP TIME (TS) AND HOLD TIME (TH) WITH RESPECT TO THIS CLOCK EDGE.
DATA INPUT SIGNAL
CLK
CLK
CLK
CLK
HI3197
HI3197
INTERNALLY 1/2
FREQUENCY-DIVIDED
SIGNAL
INTERNALLY 1/2
FREQUENCY-DIVIDED
SIGNAL
CLK
CLK
CLK
HI3197
HI3197
CLK
RESET
RESET
RESET
SIGNAL
RESET SIGNAL
(WHEN ACTIVE LOW)
INTERNALLY 1/2
FREQUENCY-DIVIDED
SIGNAL
INTERNALLY 1/2
FREQUENCY-DIVIDED
SIGNAL
HI3197
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