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參數(shù)資料
| 型號： | HI3197 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 125 MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.0035 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 284K |
| 代理商： | HI3197 |
9
Supply Current (PS Mode)
NOTE: The current consumption in power
saving mode does not include the voltage
reference (V
REF
) current. When using the in-
ternalreferencetheadditionalcurrentI
REF
=
V
REF
/ R
REF
should be added to the table
values for an accurate estimate of total
standby current.
I
CC
DI
CC1
DI
CC2
AI
CC2
AI
CC0
Power Saving Mode
-
0.432
4
mA
Power Saving Mode
-
0.38
1.5
mA
Power Saving Mode
-
0.001
0.2
mA
Power Saving Mode
-
0.05
0.3
mA
Power Saving Mode
-
0.001
2
mA
Electrical Specifications
V
SUPPLY
=
±
5V, A
V
= +1, R
L
= 100
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC Specifications
MUX.1A and MUX.1B Modes
PARAMETER
CLK SIGNAL LEVEL
PECL
TTL
PECL
UNITS
RESET SIGNAL LEVEL
PECL
TTL
TTL
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MUX.1A MODE
Maximum Conversion Rate
f
C
125
-
-
100
-
-
125
-
-
MSPS
Clock High Pulse Width
t
PW1
t
PW0
t
S-RST
t
H-RST
t
D-DIV
2T-tm
3.5
-
-
4.5
-
-
3.5
-
-
ns
Clock Low Pulse Width
3.5
-
-
3.0
-
-
3.5
-
-
ns
Reset Signal Setup Time
0
-
-
1.0
-
-
4.0
-
-
ns
Reset Signal Hold Time
1.0
-
-
3.0
-
-
0
-
-
ns
DIV2OUT Output Delay
C
L
= 10pF
5.5
6.5
8
8.0
9.5
12.0
5.5
6.5
8
ns
DIV2OUTtoDIV2INMaximum
Delay Time
-
-
2T - 7
-
-
2T - 7
-
-
2T - 7
ns
Data Input Setup Time
t
S
t
H
1.0
-
-
1.0
-
-
1.0
-
-
ns
Data Input Hold Time
5.0
-
-
5.0
-
-
5.0
-
-
ns
Analog Output Pipeline Delay
t
PD
(A)
t
PD
(B)
t
DO
-
4
-
-
4
-
-
4
-
CLK
-
5
-
-
5
-
-
5
-
CLK
Analog Output Delay
5.0
5.5
6.0
6.5
7.5
8.5
5.0
5.5
6.0
ns
MUX.1B MODE
Maximum Conversion Rate
f
C
125
-
-
100
-
-
125
-
-
MSPS
Clock High Pulse Width
t
PW1
t
PW0
t
S-RST
t
H-RST
t
S
t
H
t
PD
(A)
t
PD
(B)
t
DO
3.5
-
-
4.5
-
-
3.5
-
-
ns
Clock Low Pulse Width
3.5
-
-
3.0
-
-
3.5
-
-
ns
Reset Signal Setup Time
0
-
-
1.0
-
-
4.0
-
-
ns
Reset Signal Hold Time
1.0
-
-
3.0
-
-
0
-
-
ns
Data Input Setup Time
1.0
-
-
1.0
-
-
1.0
-
-
ns
Data Input Hold Time
4.0
-
-
6.0
-
-
4.0
-
-
ns
Analog Output Pipeline Delay
-
2
-
-
2
-
-
2
-
CLK
-
3
-
-
3
-
-
3
-
CLK
Analog Output Delay
5.0
5.5
6.0
6.5
7.5
8.5
5.0
5.5
6.0
ns
AC Specifications
MUX.2, SEL.A, and SEL.B Modes
PARAMETER
CLK SIGNAL LEVEL
PECL
TTL
UNITS
RESET SIGNAL LEVEL
(NOTE 2)
(NOTE 2)
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MUX.2 MODE
Maximum Conversion Rate
f
C
125
-
-
100
-
-
MSPS
Clock High Pulse Width
t
PW1
t
PW0
t
S-DIV
3.5
-
-
4.5
-
-
ns
Clock Low Pulse Width
3.5
-
-
3.0
-
-
ns
DIV2IN Signal Setup Time
4.5
-
-
2.0
-
-
ns
HI3197
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