- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371813 > HI3197 (HARRIS SEMICONDUCTOR) 10-Bit, 125 MSPS D/A Converter PDF資料下載
參數(shù)資料
| 型號： | HI3197 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 125 MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.0035 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 284K |
| 代理商： | HI3197 |
15
MUX.1B Mode
Set C1 and C2 Low and C3 High for this mode.
In MUX.1B mode, the frequency of the clock input from the
clock input pin is halved internally, and the data is loaded by
this 1/2 frequency-divided signal. The 1/2 frequency-divided
signal cannot be observed at this time, so the data is actually
loaded by observing the clock and reset signals to estimate
the rising edge of the internally 1/2 frequency-divided signal.
The data can be divided and input to two systems: A (DA0 to
DA9) and B (DB0 to DB9). The data is internally multiplexed,
then the system A data is output as an analog signal with a
2-clock pipeline delay, and the system B data as an analog
signal with a 3-clock pipeline delay after loading by the clock.
Like MUX.1A mode, when using the multiple HI3197 in
MUX.1B mode, the start timing of the 1/2 frequency-divided
clocks becomes out of phase, producing operation such as
that shown in the example below. As a countermeasure, the
MUX.1B mode also has a function that matches the start
timing of the 1/2 frequency-divided clocks with the reset
signal. When using a PECL level reset signal, input the reset
signal to Pins 23 and 24 (RESETP/E, RESETN/E) and leave
Pin 22 (RESET/T) open. When using a TTL level reset signal,
input the reset signal to Pin 22 (RESET/T) and leave Pins 23
and 24 (RESETP/E, RESETN/E) open. The reset polarity can
be switched by the R POLARITY pin (Pin 39). When the R
POLARITY pin is High or open, reset is active Low; when
Low, reset is active High. See Figure 8 for the detailed timing.
FIGURE 7B. MUX.1A EXAMPLE WHEN NOT USING THE RESET SIGNAL
FIGURE 7C. MUX.1A EXAMPLE WHEN USING THE RESET SIGNAL
FIGURE 7. MUX.1A MODE
CLK
CLK DIV2OUT
CLK
CLKDIV2OUT
DIV2OUT
DIV2OUT
HI3197
HI3197
CLK DIV2OUT
CLK
CLKDIV2OUT
HI3197
HI3197
CLK
DIV2OUT
DIV2OUT
RESET
RESET
RESET
SIGNAL
RESET SIGNAL
(WHEN ACTIVE LOW)
HI3197
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI3276JCQ | Small glass bead with axial leads |
| HI3338KIB | TVS 6.0V 300W UNI-DIR SOT-23 |
| HI3338KIP | TVS DUAL-UNI SGL-BI 300MW SOT-23 |
| HI3338 | 8-Bit, CMOS R2R D/A Converter |
| HI4P0222-5 | High Frequency/Video Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI3197JCQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI31C | 制造商:HSMC 制造商全稱:HSMC 功能描述:NPN EPITAXIAL PLANAR TRANSISTOR |
| HI-3200 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:AVIONICS DATA MANAGEMENT ENGINE |
| HI-3200CQI | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:AVIONICS DATA MANAGEMENT ENGINE |
| HI-3200CQIF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:AVIONICS DATA MANAGEMENT ENGINE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。