參數(shù)資料
型號: HM-6504
廠商: Intersil Corporation
英文描述: 4096 x 1 CMOS RAM
中文描述: 4096 × 1 CMOS存儲器
文件頁數(shù): 7/10頁
文件大?。?/td> 167K
代理商: HM-6504
6-140
Timing Waveforms
(Continued)
The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of E
(T = 0), the addresses, the write signal, and the data input
are latched in on-chip registers. The logic value of W at the
time E falls determines the state of the output buffer for that
cycle. Since W is low when E falls, the output buffer is
latched into the high impedance state and will remain in that
state until E returns high (T = 2). For this cycle, the data
input is latched by E going low; therefore, data set up and
hold times should be referenced to E. When E (T = 2)
returns to the high state, the output buffer and all inputs are
disabled and all signals are unlatched. The device is now
ready for the next cycle.
(7)
TAVEL
(7)
TAVEL
(11)
TWLEL
(15)
TDVEL
HIGH-Z
NEXT DATA
(11)
TWLEL
(15)
TDVEL
DATA VALID
HIGH-Z
-1
TIME
0
1
2
3
4
REFERENCE
(8)
TELAX
NEXT ADD
(18) TELEL
(6) TEHEL
(5) TELEH
(6)
TEHEL
(13)
TELWH
(17)
TELDX
D
W
Q
E
A
FIGURE 2. EARLY WRITE CYCLE
ADD VALID
TRUTH TABLE
TIME REFERENCE
INPUTS
OUTPUT
FUNCTION
E
W
A
D
Q
-1
H
X
X
X
Z
Memory Disabled
0
L
V
V
Z
Cycle Begins, Addresses are Latched
1
L
X
X
X
Z
Write in Progress Internally
2
X
X
X
Z
Write Completed
3
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
4
L
V
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
HM-6504/883
相關PDF資料
PDF描述
HM-6504883 4096 x 1 CMOS RAM
HM1-6504B883 4096 x 1 CMOS RAM
HM1-6508B883 1024 x 1 CMOS RAM
HM1-6508883 1024 x 1 CMOS RAM
HM-6508 1024 x 1 CMOS RAM
相關代理商/技術參數(shù)
參數(shù)描述
HM-6504/883 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:4096 x 1 CMOS RAM
HM-6504883 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:4096 x 1 CMOS RAM
HM-6508 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024 x 1 CMOS RAM
HM-6508/883 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024 x 1 CMOS RAM
HM-6508883 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024 x 1 CMOS RAM