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參數(shù)資料
| 型號： | HM-6504 |
| 廠商： | Intersil Corporation |
| 英文描述： | 4096 x 1 CMOS RAM |
| 中文描述： | 4096 × 1 CMOS存儲器 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 167K |
| 代理商： | HM-6504 |
6-141
Timing Waveforms
(Continued)
The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.
Recall that in the early write, the output is guaranteed to
remain high impedance, and in the read-modify-write, the
output is guaranteed valid at access time. The late write is
between these two cases. With this cycle the output may
become active, and may become valid data, or may remain
active but undefined. Valid data is written into the RAM if
data setup, data hold, write setup and write pulse widths are
observed.
(7)
TAVEL
(8)
TELAX
(7)
TAVEL
(14)
TDVWL
(16)
TWLDX
DATA VALID
(4)
TEHQZ
HIGH Z
A
E
W
D
Q
-1
TIME
0
1
2
3
4
5
REFERENCE
(18) TELEL
(5) TELEH
(6)
TEHEL
(6)
TEHEL
(10)
TWLEH
(9)
TWLWH
(3)
TELQX
FIGURE 3. LATE WRITE CYCLE
NEXT ADD
ADD VALID
HIGH Z
TRUTH TABLE
TIME
REFERENCE
INPUTS
OUTPUTS
FUNCTION
E
W
A
D
Q
-1
H
X
X
X
Z
Memory Disabled
0
H
V
X
Z
Cycle Begins, Addresses are Latched
1
L
X
V
X
Write Begins, Data is Latched
2
L
H
X
X
X
Write In Progress Internally
3
H
X
X
X
Write Completed
4
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
X
Z
Cycle Ends, Next Cycle Begins (Same as 0)
HM-6504/883
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM-6504883 | 4096 x 1 CMOS RAM |
| HM1-6504B883 | 4096 x 1 CMOS RAM |
| HM1-6508B883 | 1024 x 1 CMOS RAM |
| HM1-6508883 | 1024 x 1 CMOS RAM |
| HM-6508 | 1024 x 1 CMOS RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM-6504/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:4096 x 1 CMOS RAM |
| HM-6504883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:4096 x 1 CMOS RAM |
| HM-6508 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024 x 1 CMOS RAM |
| HM-6508/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024 x 1 CMOS RAM |
| HM-6508883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1024 x 1 CMOS RAM |
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