參數(shù)資料
型號(hào): HM5251805B
廠商: Hitachi,Ltd.
英文描述: 512-Mbit SDRAM(512M位同步RAM)
中文描述: 512兆位的SDRAM(512M位同步內(nèi)存)
文件頁(yè)數(shù): 22/64頁(yè)
文件大?。?/td> 1030K
代理商: HM5251805B
HM5251165B/HM5251805B/HM5251405B-75/A6/B6
22
Operation of the SDRAM
The following chapter shows operation example of the products below.
Organization
Input/output mask
CAS
latency
8-Mword
×
16-bit
×
4 bank
16-Mword
×
8-bit
×
4 bank
32-Mword
×
4-bit
×
4 bank
DQMU/DQML
2/3
DQM
DQM
Note:
The SDRAM should be used according to the product capability (See “Features”, “Pin Description”
and “AC Characteristics”).
Read/Write Operations
Bank active:
Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to
the status of the BA0/BA1 pin, and the row address (AX0 to AX12) is activated by the A0 to A12 pins at the
bank active command cycle. An interval of t
RCD
is required between the bank active command input and the
following read/write command input.
Read operation:
A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (
CAS
Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8. The start address for a burst read is specified by the column address
and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data output starts
after the number of clocks specified by the
CAS
Latency. The
CAS
Latency can be set to 2 or 3.
When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The
CAS
latency and burst length must be specified at the mode register.
相關(guān)PDF資料
PDF描述
HM5251165B 512-Mbit SDRAM(512M位同步RAM)
HM5257405BTD-75 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5257165B 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5257165B-75 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5257165B-A6 CABLE ASSEMBLY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5257165B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5257165B-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5257165B-A6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5257165BTD-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5257165BTD-A6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 】 16-bit 】 4-bank/16-Mword 】 8-bit 】 4-bank /32-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM