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參數(shù)資料
| 型號(hào)： | HM5264405D |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| 中文描述： | 6400 LVTTL接口的SDRAM（6400 LVTTL接口同步的DRAM） |
| 文件頁(yè)數(shù)： | 10/67頁(yè) |
| 文件大小： | 615K |
| 代理商： | HM5264405D |
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HM5264165D-A60, HM5264805D-A60, HM5264405D-A60
10
V
SS
and V
SS
Q (power supply pins):
Ground is connected. (V
SS
is for the internal circuit and V
SS
Q is for
the output buffer.)
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the
CS
,
RAS
,
CAS
,
WE
and address pins.
CKE
Command
Symbol
n - 1 n
CS
RAS CAS WE
A12/A13 A10
A0
to A11
Ignore command
DESL
H
×
×
×
×
×
×
×
×
×
×
H
×
×
×
×
×
×
×
×
×
×
×
×
No operation
NOP
H
L
H
H
H
Burst stop in full page
BST
H
L
H
H
L
Column address and read command
READ
H
L
H
L
H
V
L
V
Read with auto-precharge
READ A
H
L
H
L
H
V
H
V
Column address and write command
WRIT
H
L
H
L
L
V
L
V
Write with auto-precharge
WRIT A
H
L
H
L
L
V
H
V
Row address strobe and bank active
ACTV
H
L
L
H
H
V
V
V
Precharge select bank
PRE
H
L
L
H
L
V
L
×
×
×
Precharge all bank
PALL
H
L
L
H
L
×
×
H
Refresh
REF/SELF H
V
L
L
L
H
×
Mode register set
Note:
H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
. V: Valid address input
MRS
H
×
L
L
L
L
V
V
V
Ignore command [DESL]:
When this command is set (
CS
is High), the SDRAM ignore command input
at the clock. However, the internal status is held.
No operation [NOP]:
This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]:
This command stops a full-page burst operation (burst length = full-page
(256; HM5264165D, 512; HM5264805D, 1024; HM5264405D)), and is illegal otherwise When data
input/output is completed for a full page of data, it automatically returns to the start address, and
input/output is performed repeatedly.
Column address strobe and read command [READ]:
This command starts a read operation. In
addition, the start address of burst read is determined by the column address (AY0 to AY7; HM5264165D,
AY0 to AY8; HM5264805D, AY0 to AY9; HM5264405D) and the bank select address (BS). After the
read operation, the output buffer becomes High-Z.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264165D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264805D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264405F | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264805F-75 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5264805F-A60 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264405DLTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405DLTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405DTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405DTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405F | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
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