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參數(shù)資料
| 型號： | HM5264405D |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| 中文描述： | 6400 LVTTL接口的SDRAM（6400 LVTTL接口同步的DRAM） |
| 文件頁數(shù)： | 11/67頁 |
| 文件大?。?/td> | 615K |
| 代理商： | HM5264405D |
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HM5264165D-A60, HM5264805D-A60, HM5264405D-A60
11
Read with auto-precharge [READ A]:
This command automatically performs a precharge operation
after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is
illegal.
Column address strobe and write command [WRIT]:
This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY7; HM5264165D, AY0 to AY8;
HM5264805D, AY0 to AY9; HM5264405D) and the bank select address (A12/A13) become the burst
write start address. When the single write mode is selected, data is only written to the location specified by
the column address (AY0 to AY7; HM5264165D, AY0 to AY8; HM5264805D, AY0 to AY9;
HM5264405D) and the bank select address (A12/A13).
Write with auto-precharge [WRIT A]:
This command automatically performs a precharge operation
after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is
full-page, this command is illegal.
Row address strobe and bank activate [ACTV]:
This command activates the bank that is selected by
A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High,
bank 2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]:
This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected.
If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh
operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table
section.
Mode register set [MRS]:
The SDRAM has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
DQM Truth Table
(HM5264165D)
CKE
Command
Symbol
n - 1
n
DQMU
DQML
Upper byte (DQ8 to DQ15) write enable/output enable ENBU
H
×
×
×
×
L
×
Lower byte (DQ0 to DQ7) write enable/output enable
ENBL
H
×
L
Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU
H
H
×
Lower byte (DQ0 to DQ7) write inhibit/output disable
Note:
H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
MASKL
H
×
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264165D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264805D | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264405F | 64M LVTTL interface SDRAM(64M LVTTL接口同步DRAM) |
| HM5264805F-75 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| HM5264805F-A60 | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:36; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264405DLTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405DLTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405DTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405DTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HM5264405F | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
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