參數(shù)資料
型號: HM5425801BTT-10
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
中文描述: 32M X 8 DDR DRAM, 0.8 ns, PDSO66
封裝: 0.400 INCH, PLASTIC, TSOP2-66
文件頁數(shù): 12/65頁
文件大小: 489K
代理商: HM5425801BTT-10
HM5425161B, HM5425801B, HM5425401B Series
Data Sheet E0086H20
12
Command Operation
Command Truth Table
The HM5425161B, the HM5425801B and HM5425401B recognize the following commands specified by the
CS
,
RAS
,
CAS
,
WE
and address pins. All other combinations than those in the table below are illegal.
CKE
Command
Symbol
n – 1 n
CS
RAS CAS WE
BA1 BA0 AP
Address
Ignore command
DESL
H
H
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
No operation
NOP
H
H
L
H
H
H
Burst stop in read command
BST
H
H
L
H
H
L
Column address and read command
READ
H
H
L
H
L
H
V
V
L
V
Read with auto-precharge
READA
H
H
L
H
L
H
V
V
H
V
Column address and write command
WRIT
H
H
L
H
L
L
V
V
L
V
Write with auto-precharge
WRITA
H
H
L
H
L
L
V
V
H
V
Row address strobe and bank active
ACTV
H
H
L
L
H
H
V
V
V
V
Precharge select bank
PRE
H
H
L
L
H
L
V
V
L
×
×
×
×
Precharge all bank
PALL
H
H
L
L
H
L
×
×
×
×
×
×
H
Refresh
REF
H
H
L
L
L
H
×
×
SELF
H
L
L
L
L
H
Mode register set
MRS
H
H
L
L
L
L
L
L
L
V
EMRS
H
H
L
L
L
L
L
H
L
V
Notes: 1. H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
. V: Valid address input
2. The CKE level must be kept for 1 CLK cycle (= t
CKEPW
) at least.
Ignore command [DESL]:
When
CS
is High at the cross point of the CLK rising edge and the V
REF
level,
every input are neglected and internal status is held.
No operation [NOP]:
As long as this command is input at the cross point of the CLK rising edge and the
V
REF
level, address and data input are neglected and internal status is held.
Burst stop in read operation [BST]:
This command stops a burst read operation, which is not applicable for
a burst write operation.
Column address strobe and read command [READ]:
This command starts a read operation. The start
address of the burst read is determined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9;
the HM5425801B, AY0 to AY9, AY11; the HM5425401B) and the bank select address (BA). After the
completion of the read operation, the output buffer becomes High-Z.
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PDF描述
HM5425401BTT-10 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425161B 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425401B 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425801B 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425161BTT-75A 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
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HM5425801BTT-75B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
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