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參數(shù)資料
| 型號： | HN29W256AH03TE |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Controller for AND Flash Memory(AND型閃速存儲器控制器) |
| 中文描述： | 控制器及快閃記憶體（及型閃速存儲器控制器） |
| 文件頁數(shù)： | 11/73頁 |
| 文件大?。?/td> | 239K |
| 代理商： | HN29W256AH03TE |
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HN29W256AH03TE-1
11
Flash Memory Interface Pin Explanation
Signal name
Direction Pin No.
Description
F_D_A[0] to F_D_A[7]
F_D_B[0] to F_D_B[7]
I/O
83, 82, 80, 79,
78, 77, 75, 74,
54, 53, 52, 50,
45, 44, 43, 42
This bus is used as command, address and data bus
for flash memory.
F_CEB[0] to F_CEB[7]
O
59, 60, 61, 62,
63, 64, 66, 67
Flash chip enable is used to select the flash memory.
F_OE_A0B, F_OE_A1B,
F_OE_B0B, F_OE_B1B
O
84, 85, 55, 56
Flash output enable is used to control read data
output from the flash memory.
F_WE_A0B, F_WE_A1B,
F_WE_B0B, F_WE_B1B
O
70, 71, 38, 39
Flash write enable is used to strobe command and
address. The command and address are latched at
the rising edge of the flash write enable.
F_SC_A0, F_SC_A1,
F_SC_B0, F_SC_B1
O
72, 73, 40, 41
Serial clock is used to read memory data and strobe
programming data. The programming data is lached
at the rising edge of the serial clock.
F_RSTB
O
57
Flash reset must be kept at V
(VSS
±
0.2 V) while
VCC is turned on and off to prevent flash memory
from unintentional erase or programming. Flash reset
must be lept at V
(VCC
±
0.2 V) after VCC becomes
stable and flash memory is in various operation such
as programming, erase and read.
F_CDE_AB, F_CDE_BB O
68, 37
Command data enable is used to control the
multiplexed flash bus when flash write enable is
asserted. Command and data are latched when
command data is low, and address is latched when
command data enable is high.
F_RDY
I
58
Flash ready/busy is driven low by flash memory during
program or erase operation. Flash ready/busy
becomes high impedance at the completion of the
program or erase operation.
Other Pin Explanation
Signal name
Direction Pin No.
Description
XIN, XOUT
I/O
22, 23
XIN and XOUT are used to connect crystal oscillator.
PORST_
I
18
This pin is used to connect reset IC for power on
reset.
TEST1
I
17
TEST1 is used for diagnostic test, and should be kept
at VDD.
TEST2 to TEST16
I
19, 20, 26, 27,
28, 29, 30, 31,
32, 33, 35, 36,
47, 86, 110
TEST2 to TEST16 are used for diagnostic test, and
should be open.
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相關代理商/技術參數(shù) |
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| HN29W256H02TE-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
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| HN29W3221T-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AND Flash EEPROM |
| HN29W3221T-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AND Flash EEPROM |
| HN29W51214ST | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash Application Design Guidelines Others |
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