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參數(shù)資料
| 型號(hào)： | HSP45106JC-25Z |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC NCO 25.6MHZ 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 數(shù)控振蕩器（NCO） |
| 頻率： | 25.6MHz |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 180mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 安裝類型： | 表面貼裝 |
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6
FN2809.8
October 16, 2008
Input Section
The Input Section loads the data on C(15:0) into one of the
seven input registers, the LSB and MSB Center Frequency
Input Registers, the LSB and MSB Offset Frequency
Registers, the LSB and MSB Timer Input Registers, and the
Phase Input Register. The destination depends on the state of
A(2:0) when CS and WR are low (Table 1).
Once the Input Registers have been loaded, the control inputs
ENCFREG, ENOFREG, ENTIREG, ENCTIREG, and
ENPOREG will allow the Input Registers to be downloaded to
the PFCS Control Registers with the input CLK. The control
inputs are latched on the rising edge of CLK and the Control
Registers are updated on the rising edge of the following CLK.
For example, to load the Center Frequency Register, the data
is loaded into the LSB and MSB Center Frequency Input
Register, and ENCFREG is set to zero; the next rising edge of
CLK will pass the registered version of ENCFREG,
R.ENCFREG, to the clock enable of the Center Frequency
Register; this register then gets loaded on the following rising
edge of CLK. The contents of the Input Registers are
downloaded to the Control Registers every clock, if the control
inputs are enabled.
Phase Accumulator Section
The Phase Accumulator adds the 32-bit output of the
Frequency Adder with the contents of a 32-bit Phase
Accumulator Register on every clock cycle. When the sum
causes the adder to overflow, the accumulation continues with
the least significant 32 bits of the result.
Initializing the Phase Accumulator Register is done by putting
a low on the INITPAC and ENPHAC lines. This zeroes the
feedback path to the accumulator, so that the register is
loaded with the current value of the Frequency Adder on the
next clock.
The frequency of the quadrature outputs is based on the
number of clock cycles required to step from 0 to full scale.
The number of steps required for this transition depends on
the phase increment calculated by the frequency adder. For
example, if the Center and Offset Frequency Registers are
programmed such that the output of the Frequency Adder is
4000 0000 hex, the Phase Accumulator will step the phase
from 0° to 360° every 4 clock cycles. Thus, for a 30MHz CLK,
the quadrature outputs will have a frequency of 30/4MHz or
7.5MHz. In general, the frequency of the quadrature output is
where N is the 32 bits of frequency control word that is
programmed. INT[] is the integer of the computation. For
example, if the control word is 20000000 hexadecimal and the
clock frequency is 30MHz, then the output frequency would
be fCLK/8, or 3.75MHz.
The Frequency Adder sums the contents of both the Center
and Offset Frequency Registers to produce a phase
increment. By enabling INHOFR, the output of the Offset
Frequency Register is disabled so that the output frequency is
determined from the Center Frequency Register alone. For
BFSK modems, INHOFR can be asserted/ de-asserted to
toggle the quadrature outputs between two programmed
frequencies. NOTE: Enabling/disabling INHOFR preserves
the contents of the Offset Frequency Register.
The Block Diagram shown in Figure 2 illustrates the method of
reading the phase accumulator of the NCO16 from a
microprocessor. The setup shown is very similar to that used
when the part is used for generating a complex sinusoid,
except that the internal SIN/COS lookup is bypassed by
setting the TEST pin to a logic 1(high). While the TEST pin is
high, the phase accumulator continues to drive the inputs of
the SIN/COS Generator while the most significant 28 bits of
the phase accumulator are multiplexed out onto the output
pins. Because of this, the part can be operated in two modes,
one where the SIN/COS Generator is permanently bypassed,
and one where the phase accumulator output is brought out to
the outputs as a check.
Figure 2 illustrates a circuit for reading out the phase
accumulator all the time. In this case, a microprocessor loads
the frequency and phase registers of the NCO16. This is fairly
straightforward, except for the Start Logic Block, which needs
to be synchronous to the oscillator clock and the
microprocessor interface. This has been left as an undefined
function, since it is dependent on the implementation. Also
note that all COS outputs (COS(15:0)) are connected,
although only COS(15:4) are valid in this application. The
microprocessor reads the sine and cosine data busses as if
TABLE 1. ADDRESS DECODE MAPPING
MOD(2:0) DECODING
A2
A1
A0
CS
WR
FUNCTION
0
↑
Load least significant bits of
Center Frequency input.
0
1
0
↑
Load most significant bits of
Center Frequency input.
0
1
0
↑
Load least significant bits of
Offset Frequency input.
0
1
0
↑
Load most significant bits of
Offset Frequency input.
1
0
↑
Load least significant bits of
Timing Interval input.
1
0
1
0
↑
Load most significant bits of
Timing Interval input.
1
0
↑
Load Phase Register
1
0
↑
Reserved
X
1
X
Input Disabled
(EQ. 1)
F
LO
Nf
CLK
×
2
32
(), or
=
N
INT
f
OUT
f
CLK
-------------
2
32
,
=
(EQ. 2)
HSP45106
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| HSP45106JC-33 | 功能描述:可編程振蕩器 16 BIT NUMERICALLY CONTROLLED OSC., 84 P RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45106JC-33Z | 功能描述:可編程振蕩器 W/ANNEAL 16 BIT CONTROLLED OSC 84 P RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45106JI-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| HSP45116 WAF | 制造商:Intersil Corporation 功能描述: |
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