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參數(shù)資料
| 型號： | HSP45106JC-25Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC NCO 25.6MHZ 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 數(shù)控振蕩器（NCO） |
| 頻率： | 25.6MHz |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 180mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 安裝類型： | 表面貼裝 |
3
FN2809.8
October 16, 2008
ENPHAC
I
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENPHAC enables the clocking of data into the Phase Accumulator Register.
ENTIREG
I
Timer Increment Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENTIREG enables the clocking of data into the Timer Increment Register.
INHOFR
I
Inhibit Offset Frequency Register Output (active low). Registered on chip by CLK. When active, after being clocked
onto chip, INHOFR zeroes the data path from the Offset Frequency Register to the Frequency Adder. New data
can be still clocked into the Offset Frequency Register. INHOFR does not affect the contents of the register.
INITPAC
I
Initialize Phase Accumulator (active low). Registered on chip by CLK. Zeroes the feedback path in the Phase
Accumulator. Does not clear the Phase Accumulator Register.
MOD(2:0)
I
Modulation Control Inputs. When selected with the PMSEL line, these bits add an offset of 0, 45, 90, 135, 180,
225, 270, or 315 degrees to the current phase (i.e., modulate the output). The lower 13 bits of the phase control
are set to zero. These bits are registered when the Phase Offset Register is enabled.
PMSEL
I
Phase Modulation Select input. Registered on-chip by CLK. This input determines the source of the data clocked
into the Phase Offset Register. When high, the Phase Input Register is selected. When low, the external
modulation pins (MOD(2:1)) control the three most significant bits of the Phase Offset Register and the 13 least
significant bits are set to zero.
PACI
I
Phase Accumulator Carry Input (active low). Registered on-chip by CLK.
INITTAC
I
Initialize Timer Accumulator (active low). This input is registered on chip by CLK. When active, after being clocked
onto chip, INITTAC enables the clocking of data into the Timer increment Register, and also zeroes the feedback
path in the Timer Accumulator.
TEST
I
Test Select Input. Registered on chip by CLK. This input is active high. When active, this input enables test busses
to the outputs instead of the sine and cosine data.
PAR/SER
I
Parallel/Serial Output Select. This input is registered on chip by CLK. When low, the sine and cosine outputs are
in serial mode. The Output Shift Registers will load in new data after ENPHAC goes low and will start shifting the
data out after ENPHAC goes high. When this input is high, the Output Registers are loaded every clock and no
shifting takes place.
BINFMT
I
Format. This input is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted to form an
offset binary (unsigned) number.
OES
I
Three-state control for bits SIN(15:0). Outputs are enabled when OES is low.
OEC
I
Three-state control for bits COS(15:0). Outputs are enabled when OEC is low.
TICO
O
Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is generated by the
Timer Accumulator.
DACSTRB
O
DAC Strobe (active low). In serial mode, this output will go low when the first bit of a new output word is valid at
the shift register output. This pin is active only in serial mode.
SIN(15:0)
O
Sine Output Data. When parallel mode is enabled, data is output on SIN(15:0). When serial mode is enabled,
output data bits are shifted out of SIN15 and SIN0. The bit stream on SIN15 is provided MSB first while the bit
stream on SIN0 is provided LSB first.
COS(15:0)
O
Cosine Output Data. When parallel mode is enabled, data is output on COS(15:0). When serial mode is enabled,
output data bits are shifted out of COS15 and COS0. The bit stream on COS15 is provided MSB first while the bit
stream in COS0 is provided LSB first.
Index Pin
Used to align chip in socket or on circuit board. Must be left as a no connect in circuit. (CPGA Package only).
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
HSP45106
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| HSP45106JC-33 | 功能描述:可編程振蕩器 16 BIT NUMERICALLY CONTROLLED OSC., 84 P RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45106JC-33Z | 功能描述:可編程振蕩器 W/ANNEAL 16 BIT CONTROLLED OSC 84 P RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
| HSP45106JI-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP45116 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Numerically Controlled Oscillator/Modulator |
| HSP45116 WAF | 制造商:Intersil Corporation 功能描述: |
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