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參數(shù)資料
| 型號： | HSP45106JC-25Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC NCO 25.6MHZ 84-PLCC |
| 標準包裝： | 90 |
| 類型： | 數(shù)控振蕩器（NCO） |
| 頻率： | 25.6MHz |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 180mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 包裝： | 管件 |
| 供應商設備封裝： | 84-PLCC（29.21x29.21） |
| 安裝類型： | 表面貼裝 |
12
FN2809.8
October 16, 2008
AC Electrical Specifications
VCC = 5.0V ±5%, TA = 0°C to +70°C (Note 5). Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
SYMBOL
NOTES
25.6MHz
33MHz
UNITS
MIN
MAX
MIN
MAX
CLK Period
tCP
39
-
30
-
ns
CLK High
tCH
15
-
12
-
ns
CLK Low
tCL
15
-
12
-
ns
WR Period
tWP
39
-
30
-
ns
WR High
tWH
15
-
12
-
ns
WR Low
tWL
15
-
12
-
ns
Setup Time A(2:0), CS to WR Going High
tAWS
13
-
13
-
ns
Hold Time A(2:0), CS from WR Going High
tAWH
1
-
1
-
ns
Setup Time C(15:0) to WR Going High
tCWS
15
-
15
-
ns
Hold Time C(15:0) from WR Going High
tCWH
0
-
0
-
ns
Setup Time WR High to CLK High
tWC
(Note 6)
16
-
12
-
ns
Setup Time MOD(2:0) to CLK Going High
tMCS
15
-
15
-
ns
Hold Time MOD(2:0) from CLK Going High
tMCH
0
-
0
-
ns
Setup Time ENPOREG, ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC,
BINFMT, TEST, PAR/SER, PACI, INITTAC
to CLK Going High
tECS
12
-
12
-
ns
Hold Time ENPOREG, ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC,
BINFMT, TEST, PAR/SER, PACI, INITTAC
from CLK Going High
tECH
0
-
0
-
ns
CLK to Output Delay SIN(15:0), COS(15:0), TICO
tDO
-
18
-
15
ns
CLK to Output Delay DACSTRB
tDSO
2
18
2
15
ns
Output Enable Time
tOE
-
12
-
12
ns
Output Disable Time
tOD
(Note 7)
-
15
-
15
ns
Output Rise, Fall Time
tRF
(Note 7)
-
8
-
8
ns
NOTES:
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK)
2.0V; all others 1.5V. Output load per test load circuit with switch closed and CL = 40pF. Output transition is measured at VOH > 1.5V and VOL
< 1.5V.
6. If ENOFREG, ENCFREG, ENTIREG, or ENPOREG are active, care must be taken to not violate setup and hold times to these registers when
writing data into the chip via the C(15:0) port.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
HSP45106
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