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參數(shù)資料
| 型號(hào)： | HSP45106JC-25Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 0K |
| 描述： | IC OSC NCO 25.6MHZ 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 數(shù)控振蕩器（NCO） |
| 頻率： | 25.6MHz |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 180mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 安裝類型： | 表面貼裝 |
7
FN2809.8
October 16, 2008
they were RAMs, using the decoded address bus to select
one or the other.
The timing for loading the Center Frequency Register (MSB
and LSB) and data being output on COS(15:0) and SIN(15:0)
is shown in Figure 3. This timing is independent of whether
the output data represents the phase accumulator data or the
SIN/COS Generator output.
When it is desired for the output of the NCO16 to be switched
back and forth between sine/cosine and the phase
accumulator, a circuit such as the one shown in Figure 4 could
be used. In this case, the sinusoidal output cannot be
interrupted, so the phase accumulator must be read out
between samples. This is possible due to the fact that the
TEST signal is simply the control line for a multiplexer on the
output of the SIN/COS Generator, but carries with it a
limitation on the maximum possible clock rate. Since TEST is
a synchronous input, the output of the NCO16 must be either
driven by the SIN/COS Generator or the phase accumulator
for an entire clock cycle. Therefore, the part must be driven at
twice the desired speed at all times so there is a clock cycle
available for TEST, when necessary. Note that the processor
must be driven from the same clock that generates the NCO
clock in order to maintain synchronous operation.
MOD0(2:0)
PMSEL
C(15:0)
WR
A(2:0)
CS
ENPOREG
ENCFREG
ENOFREG
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
SIN0-15
COS(15:0)
OES
OEC
HSP45106
DECODE
MICROPROCESSOR
DATA
WE
ADDRESS
GND
VCC
START
LOGIC
OSCILLATOR
FIGURE 2. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NCO16
(15:0)
WR
A0-2
ENCFREG,
ENOFREG
COS0-15,
SIN0-15
TRANSFER DATA
TO CENTER OR OFFSET
FREQUENCY REGISTER
NEW
FREQUENCY
DATA
CS
FIGURE 3. NCO16 PIPELINE DELAY
CLK
WRITE
REGISTER
WRITE
LS INPUT
REGISTER
MS INPUT
C0-15
MOD0-2
PMSEL
C0-15
WR
A0-2
CS
ENPOREG
ENCFREG
ENOFREG
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
SIN0-15
COS0-15
OES
OEC
HSP45106
DECODE
MICROPROCESSOR
DATA
WE
ADDRESS
GND
VCC
OSCILLATOR
÷2
REGISTER
DAC
>
FIGURE 4. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NCO16 WHILE GENERATING SINUSOID
START
LOGIC
HSP45106
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| HSP45106JC-33 | 功能描述:可編程振蕩器 16 BIT NUMERICALLY CONTROLLED OSC., 84 P RoHS:否 制造商:IDT 封裝 / 箱體:5 mm x 7 mm x 1.5 mm 頻率:15.476 MHz to 866.67, 975 MHz to 1300 MHz 頻率穩(wěn)定性:+/- 50 PPM 電源電壓:3.63 V 負(fù)載電容:10 pF 端接類型:SMD/SMT 輸出格式:LVPECL 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 尺寸:7 mm W x 5 mm L x 1.5 mm H 封裝: |
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| HSP45106JI-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| HSP45116 WAF | 制造商:Intersil Corporation 功能描述: |
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