參數(shù)資料
型號(hào)： HSP50214AVC
廠商： HARRIS SEMICONDUCTOR
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁(yè)數(shù)： 37/60頁(yè)
文件大?。?/td> 467K
代理商： HSP50214AVC
37
Buffer RAM Output Port
The Buffer RAM parallel output mode utilizes a RAM to store
output data for future retrieval by either the 8-bit microproces-
sor that is configuring the PDC or by a 16-bit baseband pro-
cessing engine (which could also be a microprocessor). Data
is output from the RAM only on request and can be obtained
from either the 8-bit
μ
P interface or from a 16-bit interface that
uses the two LSBytes of AOUT and BOUT. The RAM holds up
to eight 80-bit sample sets. Each sample set includes 16 bits
of each I, Q, magnitude, phase, and frequency data. The
RAM samples are mapped as shown in Table 16. The Buffer
RAM controller supports both FIFO and Snapshot modes.
The FIFO mode allows the processor to service the interface
only when enough samples are present in the RAM. This
mode is provided so that the
μ
Processor does not have to
service the PDC every output sample. An interrupt,
INTRRPT, is asserted when the desired number of samples
are available. The PDC can be programmed to assert the
interrupt when up to 7 samples are available. Control Word
21, Bit 15 is used to set the Buffer RAM controller to the
FIFO mode, while Control Word 21, Bits 12-14 set the num-
ber of RAM samples to be stored (0 to 7) before the interrupt
(INTRRPT) is asserted. Control Word 20, Bit 24 determines
whether the RAM output interface is the 8-bit microprocessor
interface or the 16-bit processor interface. In the 16-bit inter-
face the MSByte is sent to AOUT(7:0) while the LSByte is
sent to BOUT(7:0).
The INTRRP output signal goes low for 8 PROCCLK cycles
when the number of samples in the Buffer RAM (depth)
reaches the programmed depth. The depth of the RAM is
calculated using Equation 23. A DSP microprocessor or the
data processing engine can use the INTRRP signal to know
that the RAM is ready to be read.
FIFO Operation via 16-Bit
μ
Processor
Interface
Figure 37 shows the conceptual configuration of the 16-bit
μ
Processor interface. This interface looks like a 16-bit
μ
Pro-
cessor read-only microprocessor interface. The SEL(2:0)
lines are the address bus and the OEAL and OEBL lines are
the read lines. The address is decoded as shown in
Table 17.
Use of the 16-bit interface for Buffer RAM output requires
Control Word 20, Bit 25, to be set to a logic “0” and Control
Word 20, Bit 24, to be set to a logic “1”. Once the Control
Word 20 has been set to route data to AOUT(7:0) and
BOUT(7:0), then the microprocessor must place a value on
the PDC input pins SEL(2:0), to choose which data type will
be output on AOUT(7:0) and BOUT(7:0). Table 17 defines
the data types in terms of SEL(2:0). With the control lines
set, the selected data is read MSByte on AOUT(7:0) and
LSByte on BOUT(7:0) when OEAL and OEBL (are low).
New data only read when OEBL goes low, so use
μ
P for 8-
bit modes. Programming SEL(2:0) = 110 outputs a 16-bit
status signal on AOUT and BOUT. The FIFO status includes
FULL, EMPTY, FIFO Depth, and READYB. These status sig-
nals are defined in Table 18.
TABLE 16. RAM DATA STORAGE MAP
RAM
SAMPLE
SET
I
DATA
(000)
Q
DATA
(001)
|r|
DATA
(010)
Φ
DATA
(011)
F
DATA
(100)
0
I
0
(15:0)
Q
0
(15:0)
|r|
0
(15:0)
φ
0
(15:0)
f
0
(15:0)
1
I
1
(15:0)
Q
1
(15:0)
|r|
1
(15:0)
φ
1
(15:0)
f
1
(15:0)
2
I
2
(15:0)
Q
2
(15:0)
|r|
2
(15:0)
φ
2
(15:0)
f
2
(15:0)
3
I
3
(15:0)
Q
3
(15:0)
|r|
3
(15:0)
φ
3
(15:0)
f
3
(15:0)
4
I
4
(15:0)
Q
4
(15:0)
|r|
4
(15:0)
φ
4
(15:0)
f
4
(15:0)
5
I
5
(15:0)
Q
5
(15:0)
|r|
5
(15:0)
φ
5
(15:0)
f
5
(15:0)
6
I
6
(15:0)
Q
6
(15:0)
|r|
6
(15:0)
φ
6
(15:0)
f
6
(15:0)
7
I
7
(15:0)
Q
7
(15:0)
|r|
7
(15:0)
φ
7
(15:0)
f
7
(15:0)
NOTE: I and Q are sample aligned in time. |r| and
φ
are sample
aligned in time, but one sample delayed from I or Q. The
frequency sample is delayed in time from I or Q by 1
sample time + 63 tap FIR impulse response. If the FIR is
set to decimate, the FIR output will be repeated every
sample time until a new value appears at the filter output.
(i.e., the frequency samples are clocked out at the I, Q
sample rate regardless of decimation.)
(EQ. 23)
D
RAM
ADDR
WRITE
ADDR
READ
–
(
)
1
]
MOD8
–
[
=
TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS
SEL(2:0)
OUTPUT DATA TYPE
000
I Data
001
Q Data
010
Magnitude
011
Phase
100
Frequency
101
Unused
110
Memory Status
111
Reading this address increments to the next
sample set
FIGURE 37. 16-BIT MICROPROCESSOR INTERFACE
BUFFER RAM MODE BLOCK DIAGRAM
|r|
φ
Q
DUAL
PORT
RAM
16
SEQUENCER
INCR
WR
“SEADDRESS
16
16
16
D
D
16
I
RD
INCR
WRITE
SEQUENCER
|r|
φ
STATUS
Q
I
0
1
2
3
4
6
OEBL
SEL(2:0)
NEW
DATA
OUTPUT
DATA
M
M
PROCCLK
HSP50214A
相關(guān)PDF資料
PDF描述
HSP50214AVI Programmable Downconverter
HSP50214B Programmable Downconverter
HSP50214BVC Programmable Downconverter
HSP50214BVI Programmable Downconverter
HT84 ADSL Coupling Transformers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP50214AVI 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214B 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214B_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214BVC 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214BVCZ 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*