參數(shù)資料
型號(hào)： HT9580
廠商： Holtek Semiconductor Inc.
英文描述： Character Pager Controller
中文描述： 字符傳呼機(jī)控制器
文件頁(yè)數(shù)： 45/63頁(yè)
文件大?。?/td> 444K
代理商： HT9580
HT9580
45
April 28, 2000
Preliminary
Interrupt System
The HT9580 is capable of directly addressing
64 Kbytes of memory. The address space has
special significance within certain addressing
modes, as follows:
Reset and interrupt vectors
The reset and interrupt vectors use the major-
ity of the fixed addresses between FFFA and
FFFF.
Stack
The stack may use memory from 01D0 to 01FF.
Theeffectiveaddressofstackandstackrelative
addressing modes will always be within this
range.
Interrupt request
IRQ
This CMOS compatible signal requests that an
interrupt sequence begin within the
IRQ is sampled during PHI2 operation; if the
interrupt flag in the processor status register is
0, the current instruction is completed and the
interrupt sequence begins during PHI1. The
program counter and processor status register
are stored in the stack. The C will then set the
interrupt mask flag high so that no further in-
terrupts may occur. At the end of this cycle, the
PCL will be loaded from address FFFE, and
PCH from location FFFF, transferring program
control to the memory vector located at these
addresses. The IRQ signal going low causes 3
bytes of information to be pushed onto the stack
before jumping to the interrupt handler. The
first byte is the high byte in the program coun-
ter. The second byte is the program counter low
byte. The third byte is the status register value.
These values are used to return the processor to
its original state prior to the IRQ interrupt.
C. The
Non-maskable interrupt
NMI
A negative-going edge on this input requests
that a non-maskable interrupt sequence be
generated within the
C. The NMI is sampled
during PHI2; the current instruction is com-
pleted and the interrupt sequence begins dur-
ing PHI1. The Program Counter is loaded with
the interrupt vector from locations FFFA (low
byte) and FFFB (high byte), thereby transfer-
ring program control to the non-maskable in-
terrupt routine. The NMI is generated from
data ready interrupt or battery fail interrupt
flag (0006H). However, it should be noted that
this is an edge-sensitive input. As a result, an-
other interrupt will occur if there is another
negative-going transition and the program has
not returned. Also, no interrupt will occur if
NMI is low and a negative-going edge has not
occurred since the last non-maskable interrupt.
The NMI signal going low causes 3 bytes of in-
formation to be pushed onto the stack before
jumping to the interrupt handler. The first byte
is the high byte in the program counter. The
second byte is the program counter low byte.
The third byte is the status register value.
These values are used to return to its original
state prior to NMI interrupt.
Data address space
The CinternaladdressbusconsistsofA0~A15
forming a 16-bit address bus for memory and
I/O exchanges on the data bus. The output of
each address line is CMOS compatible. The Ad-
dress output pins of HT9580 (A0~A15) derive
from C internal address pins A0~A15. The ex-
tended address pins (RA14~RA18) are the com-
bination of bank point registers (0015H,
0016H) and internal address. The extended ad-
dress pins are used to access internal/external
SRAM or Mask ROM (Character ROM).
The data lines constitute 8-bit bidirectional
data bus for use during exchanges between the
C and peripherals. The outputs are
three-state buffers capable of driving CMOS
load. The Program Address and Data Address
space is continuous throughout the 64 Kbyte
address space. Words, arrays, records, or any
data structures may span the 64 Kbytes ad-
dress space. The following addressing mode de-
scriptions provide additional detail as to how
effective addresses are calculated. Fifteen ad-
dressing modes are available for the HT9580 as
illustrated on the next page.
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