HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 15 - 1999 Hyundai System IC Division
PRELIMINARY
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Pixel bias voltage register[8’h34]
The register controls pixel analog voltage decrement degree by controlling bias current of pixel output
sensing load transistor. With the reset level register(8’ h30) it is used to adjust ADC circuit output
characteristics. The larger register value causes the higher bias current to increase pixel output
decrement degree, and commonly the register default value is used. Program value range is 0~7.
RSET LEVEL STATISTICS REGISTER
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Low Reset Level Count[8’h57-8’h58]
This two-byte register has a value representing a eighth (1/8) of pixels that have reset value less than 3
during one frame time and is updated when VSYNC gets active. With high reset level counter register it
can be used as a parameter for external automatic reset level control logic that update the appropriate
value in the reset level register to automatically compensate die to die overall reset level variation.
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High Reset Level Count[8’h59-8’h5a]
This two byte register has a value representing a eighth (1/8) of pixels that have reset value larger than
123 during one frame time and is updated when VSYNC gets active. With low reset level counter register
it can be used as a parameter for external automatic reset level control logic that update the appropriate
value in the reset level (30H) register to automatically compensate die to die overall reset level variation.
RGB OFFSET REGISTERS[8’h50-8’h52]
These registers control offset value of RGB digital output to make color effect. Normally these register
values are set to default zero.