參數(shù)資料
型號: HV7131B
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS IMAGE SENSOR With 8-bit ADC
中文描述: CMOS圖像傳感器的8位ADC
文件頁數(shù): 24/29頁
文件大?。?/td> 834K
代理商: HV7131B
HV7131B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31991011R_1.0 - 24 - 1999 Hyundai System IC Division
PRELIMINARY
2. Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress = 3; WindowHeight = 482;
ColumnStartAddress = 3; WindowWidth = 642;
IntegrationTime = 600 [Line Mode];
EffectiveWindowHeight is “482” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e.
488 > (3 + 482 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time
< EffectiveWindowHeight * Scale), i.e. 600 > 482 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 482) *
1024 clocks idle slot, is inserted before the next frame initiation.
Overall Frames Sequence
MCLK
ENB
VSYNC
Delay
Slots
Fig. 5 Initial Data Setup Time after ENB gets active
L
ENB
Deglitch
2 clocks
Sensor Reset
SensorArrayHeight clocks
[488 clocks]
One Line Time Delay
(SensorArrayWidth +
HBLANK) clocks
[651 clocks]
VSYNC
3 clocks
Integration Time *
Scale clocks
[600 * 648 clocks]
I
L
,
L
....
L
L
L
,
L
....
V
L
L
,
L
....
L
V
I
L
V
I
I
Frame 1
Frame 2
Frame 0
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