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參數(shù)資料
| 型號(hào)： | HY5PS12423F |
| 英文描述： | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 128Mx4 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁(yè)數(shù)： | 31/66頁(yè) |
| 文件大小： | 862K |
| 代理商： | HY5PS12423F |
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Rev. 0.52/Nov. 02 31
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by
DDR-II SDRAM. In Drive(1) mode, all DQ, DQS signals are driven high and all DQS signals are driven low. In drive(0)
mode, all DQ, DQS signals are driven low and all DQS signals are driven high. In adjust mode, BL=4 of operation code
data must be used. In case of OCD calibration default, output driver characteristics follow approximate nominal V/I
curve for 18 ohm output drivers, but are not guranteed. If tighter control is required, which is controlled within 18ohm +/
- 3ohm driver impedance range, OCD must be used.
Off-Chip Driver program
OCD impedance adjust
OCD impedance adjustment can be done using “EMRS Adjust mode” and “input operation code patterns” as the fol-
lowing table. To adjust output driver impedance, controllers must issue “Adjust mode” command using an EMRS com-
mand first, after that drive 4 bit of burst code information to DDR-II SDRAM. For this operation, controllers must drive
all DQs to each device. Driver impedance in each DDR-II SDRAM device is adjusted for all DQs simultaneously. The
maximum step count for adjustment is 8 and when the limit is reached, further increment or decrement has no effect.
Default setting can be any step within the 8 step range.
Off Chip Driver Program
A9
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
1
Drive(1) DQ, DQS high and DQS low
0
1
0
Drive(0) DQ, DQS low and DQS high
1
0
0
Adjust mode
1
1
1
OCD calibration default
4bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
NOP(No operation)
NOP (No operation)
0
0
0
1
Increase by 1 step
NOP
0
0
1
0
Decrease by 1 step
NOP
0
1
0
0
NOP
Increase by1 step
1
0
0
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
Increase by1 step
0
1
1
0
Decrease by 1 step
Increase by1 step
1
0
0
1
Increase by1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Decrease by 1 step
Other Combinations
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5PS12423LF | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823LF | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5P | Current Transducers HY 5 to 25-P/SP1 |
| HY5R256HC | -|2.5V|8K|40|Direct RDRAM - 256M |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS12423LF | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12821AF | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C3 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C4 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-E3 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
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