- 您現(xiàn)在的位置：買賣IC網 > PDF目錄370740 > HY5PS12423F 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M PDF資料下載
參數(shù)資料
| 型號： | HY5PS12423F |
| 英文描述： | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 128Mx4 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內存- 512M |
| 文件頁數(shù)： | 48/66頁 |
| 文件大?。?/td> | 862K |
| 代理商： | HY5PS12423F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當前第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
Rev. 0.52/Nov. 02 48
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Precharge Opeation
The precharge command is used to close or deactivate the open row in particular bank or the open row in all banks.
Precharge command is issued by activating CS, RAS, WE and deactivating CAS at the rising edge of clock. Bank
address and A10 provided on inputs BA0~BA1, A10 selects the bank to be precharged. Input A10 determines whether
one or all banks precharge. All bank precharged command is issued with A10=high, at that case, the other bank
address inputs are don’t care. But Bank address inputs select bank to be precharged, when precharge command is
issued with A10 = low. Once a bank has been precharged, it is in the idle state and must be activated prior to any read
or write commands being issued to that bank. The bank will be available for a subsequent row access some specified
time (tRP) after the precharge command is issued. Burst termination by precharge command is prohibited.
Bank Selection for Precharge
A10
BA0
BA1
Precharged Bank
Low
Low
Low
Bank 0 only
Low
Low
High
Bank 1 only
Low
High
Low
Bank 2 only
Low
High
High
Bank 3 only
High
Don’t care
Don’t care
All Banks 0~3
相關PDF資料 |
PDF描述 |
|---|---|
| HY5PS12423LF | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823LF | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5P | Current Transducers HY 5 to 25-P/SP1 |
| HY5R256HC | -|2.5V|8K|40|Direct RDRAM - 256M |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS12423LF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12821AF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12821AF-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。