參數(shù)資料
型號: HYB 39S256160T
廠商: SIEMENS AG
英文描述: 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態(tài)RAM)
中文描述: 256兆位(4banks ×的4Mb × 16)同步DRAM(256M(4列× 4分位× 16)同步動態(tài)RAM)的
文件頁數(shù): 19/47頁
文件大?。?/td> 316K
代理商: HYB 39S256160T
HYB 39S256400/800/160T
256-MBit Synchronous DRAM
Data Book
19
12.99
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests
for LV-TTL versions
have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit shown in figure below. Specified
t
AC
and
t
OH
parameters are measured with a 50 pF only, without any resistive termination and
with a input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
t
T
/2
0.5) ns has to be added to this parameter.
4. If
t
T
is longer than 1 ns, a time (
t
T
1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock
t
AC
is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time
t
OH
is 1.8 ns for PC133 components with no termination and 0 pF load.
7. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
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