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參數(shù)資料
| 型號： | HYB18T1G160AFL-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 1 Gbit DDR2 SDRAM |
| 中文描述： | 1千兆位DDR2內(nèi)存 |
| 文件頁數(shù)： | 81/89頁 |
| 文件大小： | 1261K |
| 代理商： | HYB18T1G160AFL-5 |
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HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 81 Rev. 1.02 May 2004
8. Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
8.1 Reference Load for Timing Measurements
The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is
not intended to either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers should use IBIS or other simulation tools to correlate the tim-
ing reference load to a system environment. Manufacturers correlate to their production test conditions, generally
a coaxial transmission line terminated at the tester electronics. This reference load is also used for output slew
rate characterisation.
The output timing reference voltage level for single ended signals is the crosspoint with VTT.
The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the
complement (e.g. DQS) signal.
8.2 Slewrate Measurements
8.2.1 Output Slewrate
With the reference load for timing measurements output slew rate for falling and rising edges is measured
between VTT - 250 mV and VTT + 250 mV for single ended signals.For differential signals (e.g. DQS / DQS) out-
put slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is veri-
fied by design, but not subject to production test.
8.2.2 Input Slewrate - Differential signals
Input slewrate for differential signals (CK / CK, DQS / DQS, RDQS / RDQS) for rising edges are measured from
f.e. CK - CK = -250 mV to CK - CK = + 500 mV and from CK - CK = +250 mV to CK - CK = - 500mV for falling
edges.
8.2.3 Input Slewrate - Single ended signals
Input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level:
VREF -125 mV to VREF + 250 mV for rising edges and from VREF + 125 mV to VREF - 250 mV for falling edges.
For slew rate definition of the input and data setup and hold parameters see section 8.3 of this datasheet.
DUT
25 Ohm
Vtt = VDDQ / 2
CK, CK
Timing Reference Points
VDDQ
DQ
DQS
DQS
RDQS
RDQS
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相關代理商/技術參數(shù) |
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| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
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| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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