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參數資料
| 型號： | HYB25D128400CT-5 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數： | 11/44頁 |
| 文件大?。?/td> | 2618K |
| 代理商： | HYB25D128400CT-5 |
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HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
19
03292006-U5AN-6TI1
3.1.1
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the burst
type and is selected via bit A3. The ordering of accesses
within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 11.
TABLE 11
Burst Definition
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
20
0-1
11-0
1-0
4
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
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相關代理商/技術參數 |
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| HYB25D128400CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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| HYB25D128800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (16Mx8) DDR200 (2-2-2)? |
| HYB25D128800ATL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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