參數(shù)資料
型號(hào): HYB25D128400CT-5
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 32M X 4 DDR DRAM, 0.7 ns, PDSO66
封裝: PLASTIC, TSOP2-66
文件頁數(shù): 18/44頁
文件大?。?/td> 2618K
代理商: HYB25D128400CT-5
HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
25
03292006-U5AN-6TI1
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 18.
10) A Write command may be applied after the completion of data output.
TABLE 18
Truth Table 6: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent Auto
Precharge Support
Unit
WRITE w/AP
Read or Read w/AP
1 + (BL/2) +
t
WTR
t
CK
Write to Write w/AP
BL/2
t
CK
Precharge or Activate
1
t
CK
Read w/AP
Read or Read w/AP
BL/2
t
CK
Write or Write w/AP
CL (rounded up) + BL/2
t
CK
Precharge or Activate
1
t
CK
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