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參數(shù)資料
| 型號： | HYB25D128400CT-5 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 2618K |
| 代理商： | HYB25D128400CT-5 |
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HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
21
03292006-U5AN-6TI1
4
Truth Tables
The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate
SDRAM.
TABLE 13
Truth Table 1: Commands
1) CKE is HIGH for all commands shown exceptSelf Refresh.
V
REF must be maintained during Self Refresh operation.
2) Deselect and NOP are functionally interchangeable.
3) BA0, BA1 provide bank address and A0 - Ai provide row address.
4) BA0, BA1 provide bank address; A0 - Ai provide column address; A10 HIGH enables the Auto Precharge feature (nonpersistent), A10
LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0 - Ai provide the op-code to be written to the selected Mode
Register.
TABLE 14
Truth Table 2: DM Operation
Name (Function)
CS
RAS CAS WE Address
MNE
Note
Deselect (NOP)
H
X
NOP
No Operation (NOP)
L
H
X
NOP
Active (Select Bank And Activate Row)
L
H
Bank/Row
ACT
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
Write (Select Bank And Column, And Start Write Burst)
L
H
L
Bank/Col
Write
Burst Terminate
L
H
L
X
BST
Precharge (Deactivate Row In Bank Or Banks)
L
H
L
Code
PRE
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
H
X
AR/SR
Mode Register Set
L
Op-Code
MRS
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
1) Used to mask write data; provided coincident with the corresponding data.
Write Inhibit
HX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128400CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800AT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (16Mx8) DDR200 (2-2-2)? |
| HYB25D128800ATL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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