參數(shù)資料
型號: HYB314400BJ-50-
廠商: SIEMENS AG
英文描述: 1M x 4-Bit Dynamic RAM
中文描述: 100萬× 4位動態(tài)隨機存儲器
文件頁數(shù): 24/25頁
文件大小: 126K
代理商: HYB314400BJ-50-
HYB 314400BJ-50/-60
3.3 V 1M
×
4 DRAM
Semiconductor Group
24
1998-10-01
Test Mode
As the HYB 314400BJ is organized internally as 512k
×
8-bits, a test mode cycle using 8:1
compression can be used to improve test time. Note that in the 1M
×
4 version the test time is
reduced by 1/2 for a linear test pattern.
In a test mode “write” the data from each I/O1 pin is written into eight bits simultaneously (all “1” or
all “0”).The I/O2 - I/O4 inputs are not used for writing in test mode. In test mode “read” each I/O
output is used for indicating the test mode result. If the internal eight bits are equal, the I/O would
indicate a “1”. If they were not equal, the I/O would indicate a “0”. Note that in test mode "read"
I/O1-I/O3 are always driven to “ones”, i.e. all outputs will be “1” for a test mode “pass”. The WCBR
cycle (WE, CAS-before-RAS) puts the device into test mode. To exit from test mode, a
“CAS-before-RAS refresh”, “RAS-only refresh” or “Hidden refresh” can be used.
Addresses A10R, A10C and A0C are don‘t care during test mode.
相關(guān)PDF資料
PDF描述
HYB314400BJ-60 IC-DARLINGTON ARRAY 4UNIT RoHS Compliant: Yes
HYB 314400BJ-60 1M × 4-Bit Dynamic RAM(Fast Page Mode)(1M x 4位 動態(tài) RAM(快速頁面模式))
HYB 39S128160CT 128-Mbit(4banks × 2MBit × 16) Synchronous DRAM(128M(4列 × 2M位 × 16)同步動態(tài)RAM)
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