參數(shù)資料
型號(hào)： HYB39L128160AC-8
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128-MBIT SYNCHRONOUS LOW-POWER DRAM
中文描述： 128 - Mbit同步低功率DRAM
文件頁(yè)數(shù)： 12/49頁(yè)
文件大?。?/td> 938K
代理商： HYB39L128160AC-8
HYB 39L128160AC/T
128-MBit 3.3V Mobile-RAM
INFINEON Technologies
12
2003-02
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock edge. The mode restores word line after the refresh and no external precharge
command is necessary. A minimum
W
time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access command after the automatic refresh operation.
In Auto-Refresh mode all banks are refreshed, independendly of the fact that the partial array self-
refresh has been set or not.
6HOI5HIUHVK
The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh
command is asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external
control signals including the clock are disabled. Returning CKE to high enables the clock and
initiates the refresh exit operation. After the exit command, at least one
W
RC
delay is required prior to
any access command.
'40)XQFWLRQ
DQMx has two functions for data I/O read and write operations. During reads, when it turns to
“
high
”
at a clock edge, data outputs are disabled and become high impedance after two clock periods
(DQM Data Disable Latency
W
). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency
W
DQW
= zero
clocks).
6XVSHQG0RGH
During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal
clock and extends data read and write operations. One clock delay is required for mode entry and
exit (Clock Suspend Latency t
CSL
).
3RZHU'RZQ
In order to reduce standby power consumption, a power down mode is available. All banks must be
precharged before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode
is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off. The
Power Down mode does not perform any refresh operations, therefore the device can
’
t remain in
Power Down mode longer than the Refresh period (
W
) of the device. Exit from this mode is
performed by taking CKE
“
high
”
. One clock delay is required for power down mode entry and exit.
$XWR3UHFKDUJH
Two methods are available to precharge Mobile-RAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function
is initiated. The Mobile-RAM automatically enters the precharge operation after
W
WR
(Write recovery
time) following the last data in.
相關(guān)PDF資料
PDF描述
HYB39L128160AT BJAWBMSpecialty DRAMs Mobile-RAM
HYB39L128160AT-75 128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L128160AT-8 128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L128160AC-7.5 HEX DIE SET,.100/.213/.429
HYB39L256160AT-7.5 BJAWBMSpecialty DRAMs Mobile-RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB39L128160AT 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:BJAWBMSpecialty DRAMs Mobile-RAM
HYB39L128160AT-7.5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128M (8Mx16) 133MHz 3-3-3 ?
HYB39L128160AT-75 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L128160AT-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L256160AC 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 MBit Synchronous Low-Power DRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*