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參數(shù)資料
| 型號： | HYB39S128400CT-75 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128-MBit Synchronous DRAM |
| 中文描述： | 128兆位同步DRAM |
| 文件頁數(shù)： | 11/51頁 |
| 文件大?。?/td> | 470K |
| 代理商： | HYB39S128400CT-75 |
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HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
11
9.01
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on, all
V
and
V
pins must be built up
simultaneously to the specified voltage when the input signals are held in the
“
NOP
”
state. The
power on voltage must not exceed
V
+ 0.3 V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200
μ
s is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is divided
into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS
Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode.
After the initial power up, the mode set operation must be done before any activate command. Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay,
t
, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is
‘
2
’
,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using sequential burst type and page length is a function
of the I/O organisation and column addressing. Full page burst operation does not self terminate
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相關代理商/技術參數(shù) |
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